EPCQ128ASI16N

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1. Features

    1. Serial or quad-serial FPGA configuration in devices that support active serial (AS) x1 or AS x4(1) configuration schemes

    2. Low cost, low pin count, and non-volatile memory

    3. 2.7-V to 3.6-V operation

    4. Available in 8-pin small-outline integrated circuit (SOIC) package for EPCQ4A, EPCQ16A, and EPCQ32A devices

    5. Available in 16-pin SOIC package for EPCQ64A and EPCQ128A devices

    6. Reprogrammable memory more than 100,000 program-erase cycles

    7. Write protection support for memory sectors using status register bits

    8. Fast read, extended dual input fast read, and extended quad input fast read of the entire memory using a single operation code

    9. Reprogrammable with an external microprocessor using the SRunner software driver

  10. In-system programming (ISP) support with the SRunner software driver

  11. By default, the memory array is erased and the bits are set to 

  12. More than 20-year data retention

  13. Supports JEDEC standard Serial Flash Discoverable Parameter (SFDP)

2. Timing Requirements

When the active low chip select (nCS) signal is driven low, shift in the operation code into the EPCQ-A device using theDATA0 pin. Each operation code bit is latched into the EPCQ-A device at rising edges of the DCLK signal. While executing an operation, shift in the desired operation code, followed by the address or data bytes. See related information for more information about the address and data bytes. The device must drive the nCS pin high after the last bit of the operation sequence is shifted in. For read operations, the data read is shifted out on the DATA[3:0] pins. You can drive the nCS pin high when any bit of the data is shifted out. For write and erase operations, drive the nCS pin high at a byte boundary, that is in a multiple of eight clock pulses. Otherwise, the operation is rejected and not executed. All attempts to access the memory contents while a write or erase cycle is in progress are rejected, and the write or erase cycle continues unaffected.

3. Write Status Operation

The write status operation does not affect the write enable latch and write in progress bits. You can use the write status operation to set the status register block protection and top or bottom bits. Therefore, you can implement this operation to protect certain memory sectors. After setting the block protect bits, the protected memory sectors are treated as read-only memory. You must execute the write enable operation before the write status operation.

4. Programming and Configuration File Support

The Intel Quartus® Prime software provides programming support for EPCQ-A devices. When you select an EPCQ-A device, the Intel Quartus Prime software automatically generates the Programmer Object File (.pof) to program the device. The software allows you to select the appropriate EPCQ-A device density that most efficiently stores the configuration data for the selected FPGA. You can program the EPCQ-A device in-system by an external microprocessor using the SRunner software driver. The SRunner software driver is developed for embedded EPCQ-A device programming that you can customize to fit in different embedded systems. The SRunner software driver reads .rpd files and writes to the EPCQ-A devices. The programming time is comparable to the Intel Quartus Prime software programming time. Because the FPGA reads the LSB of the .rpd data first during the configuration process, the LSB of .rpd bytes must be shifted out first during the read bytes operation and shifted in first during the write bytes operation. Writing and reading the .rpd file to and from the EPCQ-A device is different from the other data and address bytes. During the ISP of an EPCQ-A device using the Intel FPGA download cables, the cable pulls the nCONFIG signal low to reset the FPGA and overrides the 10-kΩ pull-down resistor on the nCE pin of the FPGA. The download cable then uses the interface pins depending on the selected AS mode to program the EPCQ-A device. When programming is complete, the download cable releases the interface pins of the EPCQA device and the nCE pin of the FPGA and pulses the nCONFIG signal to start the configuration process. The FPGA can program the EPCQ-A device in-system using the JTAG interface with the serial flash loader (SFL). This solution allows you to indirectly program the EPCQ-A device using the same JTAG interface that is used to configure the FPGA.