14235R-2000 Integrated Circuits (ICs)

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1. DESCRIPTION

The FT 5000 Smart Transceiver includes three independent 8-bit logical processors to manage the physical MAC layer, the network, and the user application. These are called the Media-Access Control (MAC) processor, the network (NET) processor, and the application (APP) processor, respectively (see Figure 1). At higher system clock rates, there is also a fourth processor to handle interrupts. The FT 5000 Smart Transceiver supports polarity-insensitive cabling using a star, bus, daisy-chain, loop, or combination topology. Thus, installers don’t have to follow a strict set of wiring rules imposed by other networking technologies. Instead, they can install wiring in the fastest and most cost-effective manner, thereby saving time and money. Free topology wiring also simplifies network expansion by eliminating restrictions on wire routing, splicing, and device placement.

2. FEATURES

    1. 3.3V operation.

    2. Higher-performance Neuron® Core — internal system clock scales up to 80MHz.

    3. Substantial device price reduction.

    4. Serial memory interface for inexpensive external EEPROM and flash non-volatile memories.

    5. Supports up to 254 Network Variables (NVs) and 127 aliases.

    6. Low-cost surface mount FT-X3 Communications Transformer.

    7. User-programmable interrupts provide faster response time to external events.

    8. Includes hardware UART with 16-byte receive and transmit FIFOs.

    9. 7 mm x 7 mm 48-pin QFN package.

  10. Supports polarity-insensitive free topology star, daisy chain, bus, loop, or mixed topology wiring.

  11. Compliant with TP/FT-10 channels using FT 3120®/FT 3150® Smart Transceivers and FTT-10/FTT-10A/ LPT-10/LPT-11 Transceivers.

  12. 12 I/O pins with 35 programmable standard I/O models.

  13. Supports up to 42KB of application code space.

  14. 64KB RAM (44KB user-accessible) and 16KB ROM on-chip memories.

  15. Unique 48-bit Neuron ID in every device for network installation and management.

  16. Very high common-mode noise immunity.

  17. -40°C to +85°C operating temperature range.

3. Pin Description

4. Backward Compatibility

The FT 5000 Smart Transceiver is fully compliant with the TP/FT-10 channel and can communicate with devices that use Echelon’s FTT-10/FTT-10A Transceivers, FT 3120/FT 3150 Smart Transceivers, or LPT-10/LPT-11 Link Power Transceivers. The Neuron Core in the FT 5000 Smart Transceiver uses the same instruction set and architecture as the previousgeneration Neuron Core, with two new additional instructions for hardware multiplication and division. The Series 5000 Neuron Core is source code compatible with applications written for the Series 3100 Neuron Core. Applications written for the Series 3100 Neuron Core must be recompiled with the NodeBuilder® FX Development Tool or the Mini FX Evaluation Kit before they can be used with the FT 5000 Smart Transceiver. The FT 5000 Smart Transceiver uses Neuron firmware version 19. Firmware versions prior to version 19 are not compatible with the FT 5000 Smart Transceiver. The Neuron firmware is pre-programmed into the on-chip ROM. The FT 5000 Smart Transceiver can also be configured to read newer firmware from external memories, allowing the firmware to be upgraded over time.

5. Enhanced performance

Faster system clock. The clock for the internal system FT 5000 Smart Transceiver is user configurable to run from 5MHz to 80MHz. The required external crystal provides a 10MHz clock frequency, and an internal PLL boosts the frequency to a maximum of 80MHz as the internal system clock speed. The previous generation Neuron 3120/3150 Core divided the external oscillator frequency by two to create the internal system clock. The FT 5000 Smart Transceiver runs an 80MHz internal system so the clock is 16 times faster than a 10MHz Neuron 3120/3150 core running. The 5MHz internal system clock mode FT 5000 Smart Transceiver provides backward compatibility to support time-critical applications designed for use with the 10MHz FT 3150 or FT 3120 Smart Transceiver. The Neuron Core Smart Transceiver inside the FT 5000 includes a built-in hardware multiplier and divider for enhanced arithmetic performance operations. Support for more network variables. Because it uses Neuron firmware version 19, the FT 5000 smart transceiver supports up to 254 application network variables and 127 aliased Neuron managed devices. The 3100 Series Neuron Chip or Smart Transceiver Neuron firmware version 15 or earlier supports up to 62 network variables and 62 aliases for Neuron-managed devices. 3100 series chips with Neuron firmware version 16 or later support up to 254 network variables. You must use the NodeBuilder FX development tool to take advantage of 254 network variables. interrupt. The FT 5000 Smart Transceiver lets developers define applications that handle asynchronous events. Interrupts are triggered by any selected state change on 12 I/O pins, either by an on-chip hardware timer counter unit, or by an on-chip high-performance hardware system timer. An application uses Neuron C interrupt clauses to define interrupt conditions and handle interrupt task conditions. Neuron C program runs Interrupt the task whenever the interrupt condition is met. See the Neuron C Programmer's Guide for more information About writing interrupt tasks and handling interrupts. JTAG. FT 5000 Smart Transceiver Provides interface for institutes Electrical and Electronics Engineers (IEEE) Standard Test Access Port and Edge Scan Architecture Joint Test Action Group (JTAG) allows 5000 series chips to be included in production testing in the boundary scan chain of the device. Boundary Scan Description Language (BSDL) files for the FT 5000 Smart Transceiver can be downloaded from Echelon's website.