C8051F133-GQ

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1. Describe

The C8051F12x and C8051F133-GQ device families are fully integrated mixed-signal system-on-chip MCUs with 64 digital I/O pins (100-pin TQFP) or 32 digital I/O pins (64-pin TQFP). With an on-chip VDD monitor, watchdog timer and clock oscillator, the C8051F12x and C8051F133-GQ devices are truly self-contained system-on-chip solutions. All analog and digital peripherals are enabled/disabled and configured by user firmware. Flash memory can even be reprogrammed in-circuit, providing non-volatile data storage and also allowing field upgrades of the 8051 firmware. On-board JTAG debug circuitry allows for non-intrusive (without using on-chip resources) full-speed in-circuit debugging using the production MCU installed in the end application. The debugging system supports inspecting and modifying memory and registers, setting breakpoints, watchpoints, single-step, run and pause commands. All analog and digital peripherals work fine when debugging using JTAG. Each MCU is specified to operate over the industrial temperature range (–45 to +85 °C). Port I/O, RST, and JTAG pins are tolerant of input signals up to 5 V. These devices are available in 100-pin TQFP or 64-pin TQFP packages.

2. Feature

    1. Analog peripherals

       1. 10 or 12-bit SAR ADC

           - ± 1 LSB INL 

           - Programmable throughput up to 100 ksps

           - Up to 8 external inputs; programmable as singleended or differential - Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5

           - Data-dependent windowed interrupt generator

           - Built-in temperature sensor

       2. 8-bit SAR ADC (‘F12x Only)

           - Programmable throughput up to 500 ksps 

           - 8 external inputs (single-ended or differential)

           - Programmable amplifier gain: 4, 2, 1, 0.5

       3. Two 12-bit DACs (‘F12x Only)

           - Can synchronize outputs to timers for jitter-free waveform generation

       4. Two Analog Comparators

       5. Voltage Reference

       6. VDD Monitor/Brown-Out Detector

    2. On-Chip JTAG Debug & Boundary Scan

        1. On-chip debug circuitry facilitates full-speed, nonintrusive in-circuit/in-system debugging

        2. Provides breakpoints, single-stepping, watchpoints, stack monitor; inspect/modify memory and registers

        3. Superior performance to emulation systems using ICE-chips, target pods, and sockets

        4. IEEE1149.1 compliant boundary scan

        5. Complete development kit

    3. 100-Pin TQFP or 64-Pin TQFP Packaging

        1. Temperature Range: –40 to +85 °C

        2. RoHS Available

    4. High Speed 8051 µC Core

        1. Pipelined instruction architecture; executes 70% of instruction set in 1 or 2 system clocks

        2. 100 MIPS or 50 MIPS throughput with on-chip PLL

        3. 2-cycle 16 x 16 MAC engine

    5. Memory

        1. 8448 bytes internal data RAM (8 k + 256)

        2. 128 or 64 kB Banked Flash; in-system programmable in 1024-byte sectors

        3. External 64 kB data memory interface (programmable multiplexed or non-multiplexed modes)

    6. Digital Peripherals

        1. 8 byte-wide port I/O (100TQFP); 5 V tolerant

        2. 4 Byte-wide port I/O (64TQFP); 5 V tolerant

        3. Hardware SMBus™ (I2C™ Compatible), SPI™, and two UART serial ports available concurrently

        4. Programmable 16-bit counter/timer array with 6 capture/compare modules

        5. 5 general purpose 16-bit counter/timers

        6. Dedicated watchdog timer; bi-directional reset pin

    7. Clock Sources

        1. Internal precision oscillator: 24.5 MHz

        2. Flexible PLL technology

        3. External Oscillator: Crystal, RC, C, or clock

    8. Voltage Supples

        1. Range: 2.7–3.6 V (50 MIPS) 3.0–3.6 V (100 MIPS)

        2. Power saving sleep and shutdown modes

3. The highlighted features are listed below

    1. High-speed pipelined 8051 compliant CIP-51 microcontroller core

    2. In-system, full-speed, non-intrusive debug interface (on-chip)

    3. True 12-bit or 10-bit 100 ksps ADC with PGA and 8-channel analog multiplexer

    4. True 8-bit 500 ksps ADC with PGA and 8-channel analog multiplexer

    5. Two 12-bit DACs with programmable update schedule

    6. 2 loop 16 x 16 multiply and accumulate engine 

    7. 128 or 64 kB in-system programmable flash memory

    8. 8448 (8 k + 256) bytes of on-chip RAM

    9. External data memory interface with 64 kB address space

  10. SPI, SMBus/I2C and (2) UART serial interfaces implemented in hardware

  11. Five general-purpose 16-bit timers

  12. Programmable counter/timer array with 6 capture/compare modules

  13. On-chip watchdog timer, VDD monitor and temperature sensor

4. Additional features

Several key enhancements have been implemented in the CIP-51 core and peripherals to improve overall performance and ease of use for end applications. The extended interrupt handler provides 20 interrupt sources for the CIP-51 (compared to 7 for the standard 8051), allowing numerous analog and digital peripherals to interrupt the controller. Interrupt-driven systems require less MCU intervention, providing more efficient throughput. Additional interrupt sources are useful when building multitasking real-time systems. The MCU has up to 7 reset sources: onboard VDD monitor, watchdog timer, missing clock detector, voltage level detection of comparator 0, forced software reset, CNVSTR0 input pin and RST pin. The RST pin is bidirectional and can accommodate an external reset or allow an internally generated POR to be output on the RST pin. Every reset source except the VDD monitor and reset input pins can be disabled in software by the user; the VDD monitor is enabled/disabled via the MONEN pin. The watchdog timer can be permanently enabled in software after a power-on reset during MCU initialization. The MCU has an internal independent clock generator which by default is used as the system clock after any reset. If desired, the clock source can be switched on the fly to an external oscillator, which can use a crystal, ceramic resonator, capacitor, RC, or an external clock source to generate the system clock. This is useful in low power applications, allowing the MCU to run from a slow (power saving) external crystal oscillator source while periodically switching to the 24.5 MHz internal oscillator as needed. Additionally, an on-chip PLL is provided to enable higher system clock speeds for increased throughput.

5. Analog Comparators

Two analog comparators with dedicated input pins are included on-chip. The comparators have software programmable hysteresis and response time. Each comparator can generate an interrupt on a rising edge, falling edge, or both. The interrupts are capable of waking up the MCU from sleep mode, and Comparator 0 can be used as a reset source. The output state of the comparators can be polled in software or routed to Port I/O pins via the Crossbar. The comparators can be programmed to a low power shutdown mode when not in use.