74CBTLV3257DS-Q10J

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Logic - Signal Switches, Multiplexers, Decoders

The 74CBTLV3257DS-Q10J is a Quad 2:1 Multiplexer/Demultiplexer that utilizes CMOS low power, advanced silicon–gate processes for high–speed and high–output–drive capability. It contains four independent 2-Bit multiplexer/demultiplexer circuits, each with two data inputs (D₀ and D₁), two data outputs (Q₀ and Q₁), two address inputs (A and B), and one active–low enable input (E).

Aplication Field

This device finds applications in any design where a 2:1 multiplexer/demultiplexer is needed such as, address and data multiplexing in bus–oriented systems, computer interfaces, random–access memories, and data– acquisition systems.

Working Principle

The address inputs (A, B) decodes the combination of address inputs and selects one of the two data inputs (D₀, D₁) to be routed to the outputs (Q₀, Q₁), when E is LOW. When E is HIGH, all output are forced LOW. With E HIGH, both outputs are LOW, regardless of the address inputs.

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