IDT2309B-1HPGI

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IDT2309B-1HPGI is a low-power, high-performance low-skew clock generator, which consists of two PLLs, an oscillator, a voltage-controlled oscillator (VCO), digital dividers, and a power-on reset (POR) circuit. The PLLs are controlled using IDT patented Digital Phase Lock Loop (DPLL) technology. The IDT2309B-1HPGI operates from a 3.3V supply with a power-up-to-full-function configuration.

The first PLL of this clock generator uses a reference clock signal at its input. This clock signal can be a channel clock such as Ethernet, a VCXO, or an external reference oscillator. The on-chip oscillator can also be used as a reference clock. The output of this PLL is the core clock of the clock generator, which has an output frequency that is a multiple of the reference clock. In addition, this PLL has a programmable-output divider, which can be used to generate lower frequency clocks.

The second PLL of the IDT2309B-1HPGI uses the core clock from the first PLL as its reference clock. This PLL is used to generate the output clock with a frequency that is in-phase with the reference clock and with a configurable pulse width and duty cycle. In addition, this PLL has a configurable output divider, which can be used to generate additional lower frequency clocks.

The voltage-controlled oscillator (VCO) of the IDT2309B-1HPGI is controlled using the phase detector of the second PLL. The output frequency of the VCO is determined by the voltage level used to control it. This feature is used to produce multiple frequency clocks and/or to generate a spread spectrum signal to minimize electromagnetic interference (EMI).

The digital dividers of the IDT2309B-1HPGI are used to generate additional output clocks with different frequencies. These dividers can be programmed to divide the input signal by different factors. The outputs of these dividers can be synchronized to the next higher frequency clock to prevent jitter.

The power-on reset (POR) of the IDT2309B-1HPGI ensures that the clock generator is in a known and safe state when power is applied to it. This POR also allows for fast recovery from power-loss conditions. In addition, the reset circuit also provides an additional static output signal that can be used to control other components in the system.

The IDT2309B-1HPGI is suitable for applications such as Ethernet, broadband access, digital TV and media processing, FPGA reference clocks, and microprocessor clock distribution. With the built-in PLLs, digital dividers, and the voltage-controlled oscillator, the IDT2309B-1HPGI is able to generate stable, low-jitter clocks with multiple frequencies and low power consumption.

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