MAX9257GTL+

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The MAX9257GTL+ is an integrated, low power, serializer/deserializer (SERDES) device from Maxim Integrated. It is an advanced SERDES circuit. The device works as a serializer when used in one direction and as a deserializer when used in the opposite direction. The device offers data rates up to 3.2 Gbps and presents a low power interface combined with a small board size. The device supports multiple protocols such as PCI Express, SATA, and HyperTransport.

The MAX9257GT+ works by providing an asynchronous serialization and deserialization of parallel bus data. On the serial side, the device converts the serial data into an 8b/10b or 64/66b parallel data stream, while on the parallel side it converts the parallel data into 8b/10b or 64/66b serial data stream. The device also provides line rate conversion, bit rate multiplication/de-multiplexing, spread spectrum clock multiplication (SSCM) support, and protocol-level conversion and reconfiguration.

The MAX9257GT+ is comprised of the following main blocks and features:

• 8b/10b Serializer/Deserializer (S/D)
• Clock Recovery unit (CRU)
• Data Recovery unit (DRU)
• Automatic calibration technique (ACT)
• Spread Spectrum Clock Multiplication (SSCM) support

The 8b/10b serializer/deserializer seeks to generate an 8 bit wide data based on the 10-bit information stream. The 10-bit information stream is received from the upstream device and is unpacked into 8-bit information stream and transmitted to the downstream device via the serial link. The deserializer performs the opposite and takes the 8-bit information stream from the serial device and packs it into the 10-bit information stream for transmission upstream.

The clock recovery unit is responsible for recovering the source clock from the incoming data and for providing the recovered clock to the downstream device. The clock recovery circuit is a phase locked loop (PLL) that monitors the input signal and provides the recovered clock at the desired rate.

The data recovery unit is responsible for recovering the data from the incoming data stream and presenting it to the downstream device. The data recovery circuit uses an 8b/10b algorithm or 64/66b algorithm to extract the data from the incoming 10-bit or 66-bit data stream.

The automatic calibration technique (ACT) is used to ensure the accuracy of the transmit-receive timing between the serial logic and the parallel logic. The MAX9257GT+ supports the following variations of the ACT:

• Single-ended single-ended (SSEA)
• Single-ended to differential (SEDA)
• Differential to single-ended (DESA)
• Differential to differential (DEDA)

The spread spectrum clock multiplication support (SSCM) provides a method for increasing the available bandwidth without adding additional clock cycles. The SSCM support is used to spread the input clock over multiple clocks, providing improved signal quality and lower signal noise.

The MAX9257GT+ is ideally suited for high speed applications with spread spectrum clock requirements such as Personal Computer Memory Card Industry Association (PCMCIA) interface, broadband networking systems such as Gigabit Ethernet, and high speed RAMs such as Dynamic RAM (DRAM). It also provides point-to-point and point-to-multipoint communications solutions. The device is suitable for a range of applications in consumer, communication, and industrial applications.

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