XC7VX485T-1FFG1761I

Due to market price fluctuations, if you need to purchase or consult the price. You can contact us or emial to us:   sales@allicdata.com

Introduction

Virtex®-7 T and XT FPGAs are available in -3, -2, -1, and-2L speed grades, with -3 having the highest performance. The -2L devices operate at VCCINT = 1.0V and are screened for lower maximum static power. The speed specification of a -2L device is the same as the -2 speed grade. The -2G speed grade is available in devices utilizing Stacked Silicon Interconnect (SSI) technology. The -2G speed grade supports 12.5 Gb/s GTX or 13.1 Gb/s GTH transceivers as well as the standard -2 speed grade specifications. Virtex-7 T and XT FPGA DC and AC characteristics are specified in commercial, extended, industrial, and military temperature ranges. Except for the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1M speed grade military device are the same as for a -1C speed grade commercial device). However, only selected speed grades and/or devices are available in each temperature range. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications.

Available device and package combinations can be found in:

    1. 7 Series FPGAs Overview (DS180)

    2. Defense-Grade 7 Series FPGAs Overview (DS185)

This Virtex-7 T and XT FPGA data sheet, part of an overall set of documentation on the 7 series FPGAs, For more specific content, please browse our PDF Power-On/Off Power Supply Sequencing The recommended power-on sequence is VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO, and VCCO to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on sequence. If VCCINT and VCCBRAM have the same recommended voltage levels then both can be powered by the same supply and ramped simultaneously. If VCCAUX, VCCAUX_IO, and VCCO have the same recommended voltage levels then they can be powered by the same supply and ramped simultaneously.

For VCCO voltages of 3.3V in HR I/O banks and configuration bank 0:

    1. The voltage difference between VCCO and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each power-on/off cycle to maintain device reliability levels.

    2. The TVCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps.

The recommended power-on sequence to achieve minimum current draw for the GTX/GTH transceivers is VCCINT, VMGTAVCC,VMGTAVTT OR VMGTAVCC, VCCINT, VMGTAVTT. There is no recommended sequencing for VMGTVCCAUX. Both VMGTAVCC and VCCINT can be ramped simultaneously. The recommended power-off sequence is the reverse of the power-on sequence to achieve minimum current draw. If these recommended sequences are not met, current drawn from VMGTAVTT can be higher than specifications during powerup and power-down.

    1. When VMGTAVTT is powered before VMGTAVCC and VMGTAVTT – VMGTAVCC> 150 mV and VMGTAVCC <0.7V, the VMGTAVTT current draw can increase by 460 mA per transceiver during VMGTAVCC ramp up. The duration of the current draw can be up to 0.3 x TMGTAVCC (ramp time from GND to 90% of VMGTAVCC). The reverse is true for power-down.

    2. When VMGTAVTT is powered before VCCINT and VMGTAVTT – VCCINT> 150 mV and VCCINT <0.7V, the VMGTAVTT current draw can increase by 50 mA per transceiver during VCCINT ramp up. The duration of the current draw can be up to 0.3 x TVCCINT (ramp time from GND to 90% of VCCINT). The reverse is true for power-down. 

There is no recommended sequence for supplies not shown.