XCVU19P-2FSVA3824E

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1. Description

XCVU19P-2FSVA3824E architecture comprises high-performance FPGA, MPSoC, and RFSoC families that address a vast spectrum of system requirements with a focus on lowering total power consumption through numerous innovative technological advancements.

2. RF Data Converter Subsystem Overview

Most Zynq UltraScale+ RFSoCs include an RF data converter subsystem, which contains multiple radio frequency analog to digital converters (RF-ADCs) and multiple radio frequency digital to analog converters (RF-DACs). The high-precision, high-speed, power efficient RF-ADCs and RF-DACs can be individually configured for real data or in most cases can be configured in pairs for real and imaginary I/Q data. 

3. Soft Decision Forward Error Correction (SD-FEC) Overview

Some Zynq UltraScale+ RFSoCs include highly flexible soft decision FEC blocks for decoding and encoding data as a means to control errors in data transmission over unreliable or noisy communication channels. The SD-FEC blocks support low-density parity check (LDPC) decode/encode and Turbo decode for use in 5G wireless, backhaul, DOCSIS, and LTE applications. 

4. Processing System Overview

Zynq UltraScale+ MPSoCs and RFSoCs feature dual and quad core variants of the Arm Cortex-A53 (APU) with dual-core Arm Cortex-R5F (RPU) processing system (PS). Some devices also include a dedicated Arm Mali™-400 MP2 graphics processing unit (GPU).  To support the processors' functionality, a number of peripherals with dedicated functions are included in the PS. For interfacing to external memories for data or configuration storage, the PS includes a multi-protocol dynamic memory controller, a DMA controller, a NAND controller, an SD/eMMC controller and a Quad SPI controller. In addition to interfacing to external memories, the APU also includes a Level-1 (L1) and Level-2 (L2) cache hierarchy; the RPU includes an L1 cache and Tightly Coupled memory subsystem. Each has access to a 256KB on-chip memory. For high-speed interfacing, the PS includes 4 channels of transmit (TX) and receive (RX) pairs of transceivers, called PS-GTR transceivers, supporting data rates of up to 6.0Gb/s. These transceivers can interface to the high-speed peripheral blocks that support PCIe at 5.0GT/s (Gen 2) as a root complex or Endpoint in x1, x2, or x4 configurations; Serial-ATA (SATA) at 1.5Gb/s, 3.0Gb/s, or 6.0Gb/s data rates; and up to two lanes of Display Port at 1.62Gb/s, 2.7Gb/s, or 5.4Gb/s data rates. The PS-GTR transceivers can also interface to components over USB 3.0 and Serial Gigabit Media Independent Interface (SGMII).

5. I/O, Transceivers

Data is transferred on-chip and off-chip through a combination of high-performance parallel SelectIO™ interfaces and high-speed serial transceiver connections. I/O modules support cutting-edge technologies Implement memory interfaces and network protocols with flexible I/O standards and voltage support.

6. Clock and memory interface

UltraScale devices contain robust clock management circuitry, including clock synthesis, buffering, and routing components, which together provide a powerful framework to meet design requirements. Clock networks allow extremely flexible clock distribution to minimize skew, power consumption, and delays associated with clock signals. Clock management techniques are tightly integrated with dedicated memory interface circuitry to support high-performance external memory, including DDR4. In addition to parallel memory interfaces, UltraScale devices also support serial memory, such as hybrid memory cubes (HMCs).

7. Routing, SSI, Logic, Storage and Signal Processing

Configurable Logic Blocks (CLBs) with 6-input Lookup Tables (LUTs) and flip-flops, DSP slices with 27x18 multipliers, 36Kb blocks of RAM with built-in FIFO and ECC support, and 4Kx72 UltraRAM blocks (in UltraScale+ devices) are all These are connected to a large number of high-performance, low-latency interconnects. In addition to logic functions, CLBs provide shift register, multiplexer and carry logic functions and the ability to configure LUTs as distributed memory to complement the powerful and configurable block RAM. The DSP slice features a 96-bit wide XOR function, a 27-bit pre-adder, and a 30-bit A input that can perform several independent functions, including multiply-accumulate, multiply-add, and pattern detection. In addition to device interconnection, in devices using SSI technology, signals can be crossed between Super Logic Regions (SLRs) using dedicated low latency interface blocks. These combined routing resources easily support next-generation bus data widths. Virtex UltraScale+ HBM devices include up to 16GB of high-bandwidth memory.

8. Configuration, encryption and system monitoring

The configuration and encryption blocks perform many device-level functions that are critical to the successful operation of an FPGA, MPSoC, or RFSoC. This high-performance configuration module supports device configuration from external media over a variety of protocols, including PCIe, typically without the use of multifunction I/O pins during configuration. The configuration block also provides 256-bit AES-GCM decryption with the same performance as the unencrypted configuration. Additional features include SEU detection and correction, partial reconfiguration support, and battery-backed RAM or eFUSE technology for AES key storage for additional security. The system monitor monitors the physical environment with on-chip temperature and power sensors, as well as up to 17 external analog inputs. With the Zynq UltraScale+ MPSoC and RFSoC, the device boots through the Configuration and Security Unit (CSU), which supports secure boot with 256-bit AES-GCM and SHA/384 blocks. The encryption engine in the CSU can be used for user encryption after startup.

9. Migrate devices

The UltraScale and UltraScale+ families offer package compatibility, enabling users to migrate designs from one device or family to another. Any two packages with the same package identifier code are package compatible. For example, the Kintex UltraScale device in the A1156 package is package compatible with the Kintex UltraScale+ device in the A1156 package. Likewise, Virtex UltraScale devices in the B2104 package are compatible with Virtex UltraScale+ devices and Kintex UltraScale devices in the B2104 package. All valid device/package combinations are provided in the Device-Package Combinations and Maximum I/O tables of this document.