XC9572XL-10TQG100Q

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1. Describe

XC9572XL-10TQG100Q is a 3.3V CPLD suitable for high-performance, low-voltage applications in cutting-edge communication and computing systems. It consists of four 54V18 functional blocks, provides 1,600 usable gates, and has a propagation delay of 5 ns.

2. Power estimation

The power consumption in CPLD will vary greatly due to system frequency, design application and output load. To help reduce power consumption, each macro unit Can be configured for low power consumption in XC9500XL device Mode (from the default high-performance mode). In addition, the software will automatically disable unused product terms and macro units to further save power. This calculation comes from laboratory measurements An XC9500XL partly fills the 16-bit counter and allows The single output (LSB) to be enabled. Actual ICC The value varies with the design application and should be verified during normal system operation.

3. Features

    1. 5 ns pin-to-pin logic delays

    2. System frequency up to 178 MHz

    3. 72 macrocells with 1,600 usable gates

    4. Available in small footprint packages

        - 44-pin PLCC (34 user I/O pins)

        - 44-pin VQFP (34 user I/O pins)

        - 48-pin CSP (38 user I/O pins)

        - 64-pin VQFP (52 user I/O pins)

        - 100-pin TQFP (72 user I/O pins)

        - Pb-free available for all packages

    5. Optimized for high-performance 3.3V systems

        - Low power operation

        - 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals

        - 3.3V or 2.5V output capability

        - Advanced 0.35 micron feature size CMOS Fast FLASH™ technology

    6. Advanced system features

        - In-system programmable

        - Superior pin-locking and routability with Fast CONNECT™ II switch matrix

        - Extra wide 54-input Function Blocks

        - Up to 90 product-terms per macrocell with individual product-term allocation

        - Local clock inversion with three global and one product-term clocks

        - Individual output enable per output pin

        - Input hysteresis on all user and boundary-scan pin inputs

        - Bus-hold circuitry on all user pin inputs

        - Full IEEE Standard 1149.1 boundary-scan (JTAG)

    7. Fast concurrent programming

    8. Slew rate control on individual outputs

    9. Enhanced data security features

  10. Excellent quality and reliability

        - Endurance exceeding 10,000 program/erase cycles

        - 20 year data retention

        - ESD protection exceeding 2,000V

  11. Pin-compatible with 5V-core XC9572 device in the 44-pin PLCC package and the 100-pin TQFP package