72235LB15PF

72235LB15PF is an FIFO (first-in, first-out) device composed of a register array and a three-stage shift register and designed for distributed, synchronized data flow applications. It can store up to 8 bits of data, and data is read out most-recently stored first.

Application field

The 72235LB15PF is broadly used in digital data flow control applications, including circuit design, semiconductor integrated circuit testing, communication control, network switching, process control, embedded system design, computer to computer communications, memory sensing, and instrumentation control.

Working Principle

When the device is used in a circuit, the data to be stored is first loaded into the FIFO’s register array. As the data is loaded into the FIFO, it is passed through the shift register, and then stored in the register array. When the data needs to be read out, the content of the FIFO’s shift register is shifted first, and the content of the shift register is written back to the FIFO register array. Finally, the content of the register array is sent to the output.

In addition, the 72235LB15PF features three control pins: an active-low reset pin which enables the reset of the entire device, a clock enable pin which enables the transmission of data when in the active low state, and an active-low write enable pin which only enables data transmission at the active low level.

To ensure data integrity, the device offers three additional features which can be used to monitor the data transfer process: a full/empty flag pin which reflects whether the FIFO is full or empty, a buffer-full flag pin which reflects the fullness of the FIFO’s buffer, and an overflow flag pin which reflects whether the FIFO has overflowed.

Through these features, the 72235LB15PF allows designers to transfer data between two processes quickly and efficiently, ensuring that data is read and written in a timely manner.