![72V211L10PF8 Allicdata Electronics](https://files.allicdata.com/upload/common/default.jpg)
Allicdata Part #: | 72V211L10PF8-ND |
Manufacturer Part#: |
72V211L10PF8 |
Price: | $ 0.00 |
Product Category: | Integrated Circuits (ICs) |
Manufacturer: | IDT, Integrated Device Technology Inc |
Short Description: | IC FIFO SYNC 512X9 10NS 32-TQFP |
More Detail: | N/A |
DataSheet: | ![]() |
Quantity: | 1000 |
1 +: | 0.00000 |
Bus Directional: | Uni-Directional |
Base Part Number: | 72V211 |
Supplier Device Package: | 32-TQFP (7x7) |
Package / Case: | 32-LQFP |
Mounting Type: | Surface Mount |
Operating Temperature: | 0°C ~ 70°C |
FWFT Support: | No |
Retransmit Capability: | No |
Programmable Flags Support: | Yes |
Expansion Type: | Depth, Width |
Series: | 72V |
Current - Supply (Max): | 20mA |
Voltage - Supply: | 3V ~ 3.6V |
Access Time: | 6.5ns |
Data Rate: | 100MHz |
Function: | Synchronous |
Memory Size: | 4.5K (512 x 9) |
Part Status: | Obsolete |
Packaging: | Tape & Reel (TR) |
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72V211L10PF8 is a 2K-word by 11-bit FIFO (First In, First Out) memory device. It is classified as a logic device, and is used as a temporary store and transfers data between two synchronous or asynchronous systems. By adding additional flow control, it can also be used in a communications interface.
The 72V211L10PF8 is based on the “shift-register” architecture. When configured correctly, the device works as a “LIFO” (Last In, First Out). This allows for the first piece of data entered to be shifted out first. This is the opposite of a FIFO data flow, where the first data entered will be the first to be retrieved.
The 72V211L10PF8 has two input and two output connections. The two inputs are LE (Load Enable) and SEL (Select). The LE input allows data to be written into the memory and SEL selects which of the two inputs is to be written. Once data is written, the LE and SEL inputs are disabled.
The 72V211L10PF8 has two outputs: R (Read Data) and ROK (Read Data Ready). R is the actual data that is output from the memory and ROK is an output signal which indicates when the data is ready to be read. When the output data is not ready, the ROK output is in a low state. When the data is ready to be output, a high (1) state is outputted from the ROK output.
When data is written into the memory, it is first shifted into the first available register. Once all of the registers are full, the LE input is disabled and no more data can be written into the memory, until one of the registers is emptied. As data is written out, the ROK output is activated and the output data is then ready to be read.
The 72V211L10PF8 offers an asynchronous reset feature. This resets the FIFO register and clears any data that may have been left in it. The two inputs, LE and SEL are used to control the flow from one memory cell to the next. This is done by cycling the LE input until the ROK output is activated.
The 72V211L10PF8 is used in a variety of applications, including communications, data buffering, storage, and synchronous/asynchronous conversions. For example, the device can be used as a network buffer for streaming video data, or it can be used to store data from a peripheral device until it can be processed. The input/output logic of the 72V211L10PF8 allows for multiple applications that require data buffering and transfer.
In summary, the 72V211L10PF8 is a logic-based FIFO memory device used to temporarily store and transfer data between two synchronous or asynchronous systems. It features two separate inputs, LE and SEL, which control the flow of data, and two outputs, R and ROK, which deliver the data for processing. Additionally, the device offers an asynchronous reset feature, allowing for easy reset of the registers. It is used in many applications where data buffering and transfer is necessary, such as communications and synchronous/asynchronous conversions.
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