Allicdata Part #: | 72V3631L15PQF-ND |
Manufacturer Part#: |
72V3631L15PQF |
Price: | $ 0.00 |
Product Category: | Integrated Circuits (ICs) |
Manufacturer: | IDT, Integrated Device Technology Inc |
Short Description: | IC SYNCFIFO 512X36 15NS 132QFP |
More Detail: | N/A |
DataSheet: | 72V3631L15PQF Datasheet/PDF |
Quantity: | 1000 |
1 +: | 0.00000 |
Bus Directional: | Bi-Directional |
Base Part Number: | 72V3631 |
Supplier Device Package: | 132-PQFP (24.13x24.13) |
Package / Case: | 132-BQFP Bumpered |
Mounting Type: | Surface Mount |
Operating Temperature: | 0°C ~ 70°C |
FWFT Support: | Yes |
Retransmit Capability: | Yes |
Programmable Flags Support: | Yes |
Expansion Type: | Depth, Width |
Series: | 72V |
Current - Supply (Max): | 400µA |
Voltage - Supply: | 3V ~ 3.6V |
Access Time: | 10ns |
Data Rate: | 66.7MHz |
Function: | Synchronous |
Memory Size: | 18K (512 x 36) |
Part Status: | Obsolete |
Packaging: | Tray |
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The 72V3631L15PQF is a conduction enhanced FIFO memory that is designed for applications in digital data communications, USB interface, data multiplexing and DMA systems, as well as real-time data compression and decompression. This device is based on functionality from a logic-based FIFO memory. The 72V3631L15PQF utilizes a highly efficient architecture that reduces multiple write/read operations from conventional logic FIFO memories to a single operation.
The 72V3631L15PQF is a 32 bit word FIFO. An 8-bit parallel input/output port is provided for each word. The device has a fixed 1KB capacity with a write/read pointer memory containing a 256-bit pointer memory and a 32-bit counter. The output data can be synchronized to the front edge of the read clock and transferred in two clock cycles. The write pointer is incremented when a new data is written. The read pointer is incremented when output data is read from the FIFO.
The 72V3631L15PQF consists of a data buffer, a write/read pointer memory and a DMA control circuit. The data buffer is organized in 4096 bits and consists of a 1KB FIFO memory that can store up to 256 words of 32 bits. The pointer memory contains a 256-bit “latency” pointer and a 32-bit “level” counter. The write/read pointers are incremented/decremented respectively. The write pointer points to the location of data in the FIFO memory where the data needs to be written and the read pointer points to the location of data which is to be read. The address which the write pointer is pointing to is the next empty address in the FIFO memory.
The DMA control circuit is used to control the data flow inside the device. DMA is used to transfer data from one address location to another in the FIFO memory. The DMA controller provides a write acknowledge, reset and data valid signals to the device. The write acknowledge signal is used to acknowledge the writing of data into the FIFO memory, the reset signal is used to reset the DMA controller and the device, and the data valid signal is used to indicate that the data is valid and ready to be read from the FIFO memory.
The 72V3631L15PQF is appropriate for implementations where a FIFO memory is used to store data. It is suitable for systems which require low latency, high throughput and uninterrupted data flow. The device is well-suited for applications such as transmission of video and audio data, real-time data compression and decompression, 3D graphics, and USB interface. It can also be used in applications that require simple memory multiplexing.
The working principle of the 72V3631L15PQF is simple. When data is written into or read from the FIFO memory, the pointer memory is updated. When data is written, the write pointer is incremented and when data is read, the read pointer is incremented. The DMA control circuit is used to control the transfer of data from one address point in the FIFO memory to another. The 72V3631L15PQF can be used to multiplex data, providing a low latency, high throughput and uninterrupted flow of data.
The specific data is subject to PDF, and the above content is for reference
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