| Allicdata Part #: | 72V3672L15PQF-ND |
| Manufacturer Part#: |
72V3672L15PQF |
| Price: | $ 0.00 |
| Product Category: | Integrated Circuits (ICs) |
| Manufacturer: | IDT, Integrated Device Technology Inc |
| Short Description: | IC FIFO 16384X36 15NS 132QFP |
| More Detail: | N/A |
| DataSheet: |  72V3672L15PQF Datasheet/PDF |
| Quantity: | 1000 |
| 1 +: | 0.00000 |
Specifications
| Bus Directional: | Bi-Directional |
| Base Part Number: | 72V3672 |
| Supplier Device Package: | 132-PQFP (24.13x24.13) |
| Package / Case: | 132-BQFP Bumpered |
| Mounting Type: | Surface Mount |
| Operating Temperature: | 0°C ~ 70°C |
| FWFT Support: | Yes |
| Retransmit Capability: | No |
| Programmable Flags Support: | Yes |
| Expansion Type: | Width |
| Series: | 72V |
| Current - Supply (Max): | -- |
| Voltage - Supply: | 3V ~ 3.6V |
| Access Time: | 10ns |
| Data Rate: | 66.7MHz |
| Function: | Synchronous |
| Memory Size: | 576K (8K x 36 x 2) |
| Part Status: | Obsolete |
| Packaging: | Tray |
Description
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72V3672L15PQF is a part of logic FIFOs memory and belongs to the class of SRAM (Static Random Access Memory). It is the first production CMOS technology family of high-speed FIFOs, which provide high dynamic data buffering across asynchronous interface. It is designed to accommodate multiple data rate, from slow to fast speeds (up to 625Mbps).The 72V3672L15PQF has two data buses, two counter buses, two read/write signals and two FIFO empty/full signals, which are used for read and write operations. The two counter buses provide address counter, which counts up to 2K words for read and write operations. The read and write signals initiate or abort the read or write operations. The FIFO empty/full signals indicate if the FIFO is empty or full.The 72V3672L15PQF has multiple applications, including providing data buffering, data synchronization, data transmission in high speed and parallel interface. It can be used in applications like digital hardware/software protocols, video transmission, cellular communication and industrial control, etc. The working principle of the 72V3672L15PQF is based on the two signal FIFO (First-In-First-Out). It is a data storage structure in which the first data entered into the FIFO, is the first to be taken out. The 72V3672L15PQF is divided into two parts: the read part and the write part. In the read part, the first data that is entered into the FIFO is accessed through the read address bus and is delivered to output via the data bus. The read address bus is incremented each time and the new cycle begins. The write part is the same, but in the opposite direction. The data bus delivers newly written data to the FIFO and the write address bus is incremented as each new cycle begins. The FIFO has additional features, such as multiple data channels, configurable data width and address width, stackable FIFO sizes and programmable write and read thresholds. The multiple data channels are used to connect read and write data bus and control bus to the memories. The configurable data width and address width allow the FIFO to send and receive data of different sizes. The stackable FIFO sizes help the FIFO to adapt to different applications. The programmable write and read thresholds are used to indicate the FIFO is full or empty.To summarize, the 72V3672L15PQF is a part of logic FIFOs memory and is used for data buffering and transmission in high speed and parallel interface. It employs the two signal FIFO technique to handle data in the first-in-first-out style. It also supports multiple concurrent data channels, configurable data width and address width, stackable FIFO sizes, and programmable write and read thresholds.The specific data is subject to PDF, and the above content is for reference
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