8T49N004A-056NLGI

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1. Description

The 8T49N004A-056NLGI is a four output Clock Generator with selectable LVDS or LVPECL outputs. The 8T49N004A-056NLGI can generate any one of four frequencies from a single crystal or reference clock. The four frequencies are selected from the Frequency Selection Table (Table 3A) and are programmed via I2C interface. The four predefined frequencies are selected in the user application by two frequency selection pins. Note the desired programmed frequencies must be used with the corresponding crystal or clock frequency as indicated in Table 3A. Excellent phase noise performance is maintained with IDT’s Fourth Generation FemtoClock® NG PLL technology, which delivers sub-400fs RMS phase jitter.

2. Features

    1. Fourth Generation FemtoClock NG PLL technology

    2. Four selectable LVPECL or LVDS outputs via I2C

    3. CLK, nCLK input pair can accept the following differential input levels: LVPECL, LVDS, HCSL

    4. FemtoClock NG VCO Range: 1.91GHz - 2.5GHz

    5. RMS phase jitter at 156.25MHz (12kHz - 20MHz): 228fs (typical)

    6. RMS phase jitter at 156.25MHz (10kHz - 1MHz): 175fs (typical)

    7. Full 2.5V or 3.3V power supply

    8. I2C programming interface

    9. PCI Express (2.5Gb/s), Gen 2 (5Gb/s), and Gen 3 (8Gb/s) jitter compliant

  10. -40°C to 85°C ambient operating temperature

  11. Lead-free (RoHS 6) packaging

3. Applications Information

    1. LVCMOS Control Pins

        All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used.

    2. CLK/nCLK Inputs

        For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground.

    3. Crystal Inputs

        For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground.

    4. LVPECL Outputs

        All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.

    5. LVDS Outputs

        All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, there should be no trace attached.