ADSP-TS201SYBPZ050

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1. DESCRIPTION

The ADSP-TS201S TigerSHARC processor is an ultrahigh performance, static superscalar processor optimized for large signal processing tasks and communications infrastructure. The DSP combines very wide memory widths with dual computation blocks—supporting floating-point (IEEE 32-bit and extended precision 40-bit) and fixed-point (8-, 16-, 32-, and 64-bit) processing—to set a new standard of performance for digital signal processors. The TigerSHARC static superscalar architecture lets the DSP execute up to four instructions each cycle, performing 24 fixed-point (16-bit) operations or six floating-point operations. Four independent 128-bit wide internal data buses, each connecting to the six 4M bit memory banks, enable quad-word data, instruction, and I/O access and provide 33.6G bytes per second of internal memory bandwidth. Operating at 600 MHz, the ADSP-TS201S processor’s core has a 1.67 ns instruction cycle time. Using its single-instruction, multiple-data (SIMD) features, the ADSP-TS201S processor can perform 4.8 billion, 40-bit MACS or 1.2 billion, 80-bit MACS per second. 

2. FEATURES

    1. Up to 600 MHz, 1.67 ns instruction cycle rate

    2. 24M bits of internal—on-chip—DRAM memory

    3. 25 mm × 25 mm (576-ball) thermally enhanced ball grid array package

    4. Dual-computation blocks—each containing an ALU, a multiplier, a shifter, a register file, and a communications logic unit (CLU)

    5. Dual-integer ALUs, providing data addressing and pointer manipulation

    6. Integrated I/O includes 14-channel DMA controller, external port, four link ports, SDRAM controller, programmable flag pins, two timers, and timer expired pin for system integration

    7. 1149.1 IEEE-compliant JTAG test access port for on-chip emulation

    8. Single-precision IEEE 32-bit and extended-precision 40-bit floating-point data formats and 8-, 16-, 32-, and 64-bit fixed-point data formats

3. BENEFITS

    1. Provides high performance static superscalar DSP operations, optimized for telecommunications infrastructure and other large, demanding multiprocessor DSP applications

    2. Performs exceptionally well on DSP algorithm and I/O benchmarks 

    3. Supports low overhead DMA transfers between internal memory, external memory, memory-mapped peripherals, link ports, host processors, and other (multiprocessor) DSPs

    4. Eases DSP programming through extremely flexible instruction set and high-level-language-friendly DSP architecture

    5. Enables scalable multiprocessing systems with low communications overhead

    6. Provides on-chip arbitration for glueless multiprocessing

4. ADSP-TS201S processor’s architectural blocks:

    1. Dual compute blocks, each consisting of an ALU, multiplier, 64-bit shifter, 128-bit CLU, and 32-word register file and associated data alignment buffers (DABs)

    2. Dual integer ALUs (IALUs), each with its own 31-word register file for data addressing and a status register

    3. A program sequencer with instruction alignment buffer (IAB) and branch target buffer (BTB)

    4. An interrupt controller that supports hardware and software interrupts, supports level- or edge-triggers, and supports prioritized, nested interrupts

    5. Four 128-bit internal data buses, each connecting to the six 4M bit memory banks

    6. On-chip DRAM (24M bit)

    7. An external port that provides the interface to host processors, multiprocessing space (DSPs), off-chip memorymapped peripherals, and external SRAM and SDRAM

    8. A 14-channel DMA controller

    9. Four full-duplex LVDS link ports

  10. Two 64-bit interval timers and timer expired pin

  11. An 1149.1 IEEE-compliant JTAG test access port for onchip emulation