Allicdata Part #: | 497-14370-2-ND |
Manufacturer Part#: |
HCF4013YM013TR |
Price: | $ 0.12 |
Product Category: | Integrated Circuits (ICs) |
Manufacturer: | STMicroelectronics |
Short Description: | IC FF D-TYPE DUAL 1BIT 14SO |
More Detail: | N/A |
DataSheet: | HCF4013YM013TR Datasheet/PDF |
Quantity: | 1000 |
2500 +: | $ 0.10937 |
5000 +: | $ 0.10231 |
12500 +: | $ 0.09526 |
25000 +: | $ 0.09032 |
62500 +: | $ 0.08820 |
Max Propagation Delay @ V, Max CL: | 90ns @ 15V, 50pF |
Base Part Number: | 4013 |
Package / Case: | 14-SOIC (0.154", 3.90mm Width) |
Mounting Type: | Surface Mount |
Operating Temperature: | -40°C ~ 125°C (TA) |
Input Capacitance: | 5pF |
Current - Quiescent (Iq): | 20µA |
Voltage - Supply: | 3 V ~ 20 V |
Current - Output High, Low: | 6.8mA, 6.8mA |
Trigger Type: | Positive Edge |
Series: | Automotive, AEC-Q100, 4000 |
Clock Frequency: | 24MHz |
Number of Bits per Element: | 1 |
Number of Elements: | 2 |
Output Type: | Differential |
Type: | D-Type |
Function: | Set(Preset) and Reset |
Part Status: | Active |
Packaging: | Tape & Reel (TR) |
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Flip-flops (FFs) are an important type of logic device commonly used to store binary information. The HCF4013YM013TR is an example of a dual D flip-flop, a type of sequential logic device which consists of two independent flip-flops that are controlled by common clock and reset signals. This device is suitable for applications such as data retention, shift registers and counters, and can store two bits of information in each circuit. It is also suitable for use in synchronous counters and serial-to-parallel converters.
A dual D flip-flop is divided into two stages, each containing a D-type flip-flop. The first stage of each consists of four inputs: D0, D1, CLK, and CLR. The second stage consists of the same four inputs (D1, D2, CLK, and CLR), plus a Q2 output. This type of flip-flop is known as a "master-slave" flip-flop, because the output of the first stage is stored in the second stage at the CLK signal\'s rising edge. This allows verified data to be stored and accessed at the same time.
When the CLK signal is low, the stored data is retained in both stages, and the device is idle. When the CLK signal goes high (the rising edge of the pulse), the data stored in the master stage is transferred to the slave stage, and the data from the master stage is stored in the slave stage. The CLR signal is used to reset both stages, clearing any stored information, and the Q1 output can be used to obtain the stored data.
The HCF4013YM013TR is also a 3-state device. This means that, in addition to the regular inputs and outputs, it has an enable input which allows the user to control when the device is enabled or disabled. When enable is low, the outputs are in the inactive state (Z), meaning they are not active and they do not affect the logic of the circuit. When enable is high, the flip-flop will behave normally and the outputs will be driven. This feature makes the HCF4013YM013TR suitable for use in applications where the output state needs to be controlled or disabled.
The HCF4013YM013TR is an ideal device for a wide range of applications. It is suitable for use as a memory cell in memory modules, and can also be used to store data in shift registers and counters. It is also suitable for use in synchronous counters and serial-to-parallel converters. The device\'s 3-state feature makes it suitable for applications where the output needs to be dynamically enabled and disabled, such as multiplexers and demultiplexers. The device is also well-suited for use in data retention and other applications where data needs to be stored and accessed quickly.
The specific data is subject to PDF, and the above content is for reference
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