MAX9240GTM+T

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Today\'s growing digital data rates create a need for faster data transmission and advanced clock and data recovery (CDR) technology. The MAX9240GTM/MAX9240GTMB/MAX9260LTPM/MAX9260LTMB parts are high-speed dual or single serializers/deserializers that provide up to 10 Gbps operation across traces as short as six inches (152 mm) at 3.3 V or 2.5 V supplies.

The MAX9240GTM+T includes both the MAX9240GTM and MAX9240GTMB serializers/deserializers and a low-noise fanout buffer and the MAX9240GTM+T is the serializer and deserializer solution designed for use in MultiGig RT2- and RT3-initiative compatible applications. Both devices are designed to operate at 10 Gbps across traces as short as 152 mm (6 in.), and are compatible with MultiGig RT2 connector systems per the SFF-8437 standard. The combination of the MAX9240GTM+T devices allow the suspended transmission line model proven to be suitable per the MultiGig RT2 specification to be leveraged in the system.

Application Fields

The MAX9240GTM+T are designed for applications requiring high data rate transmission and reception across short traces, such as in server, storage, and high-end embedded applications. It is also suitable for 10 Gbps, 5 Gbps and 2.5 Gbps PCIe and SAS applications.

The high level of integration ensures a smaller form factor, which will help reduce board space that is critical when deploying higher data rates in a variety of applications. The integrated four-output fanout buffer is designed to provide e•cient mapping of lane, port, and side information between the board and cable.

Working Principle

The MAX9240GTM+T provide a 10 Gbps serializer/deserializer solution that operates from a single 2.5 V or 3.3 V supply voltage. The MAX9240GTM includes the serializer and operates from a single supply. The MAX9240GTMB includes the deserializer and operates from a separate supply. The MAX9240GTM and MAX9240GTMB are available in 25-bump WLP packages.

The serializer converts a 10 Gbps source differential data stream into a serial stream and the deserializer recovers a 10 Gbps source differential data stream from the serial stream. The serial stream is compatible with MultiGig RT2 connectors, which are compliant with the SFF-8437 standard.

The MAX9240GTM+T\'s low-noise fanout buffer is designed to e•ciently map lane, port, and side information between board and cable. The fanout buffer is used to divide the functions of laning, port mapping, and signal side information. The fanout buffer supports up to four differential receiver pairs and two differential transmitter pairs.

The MAX9240GTM+T devices provide low power consumption and low EMI. The power consumption for the MAX9240GTM+T devices is 2.5 V (typ) or 2.5 V (max) depending on the part. The chip has a power reduction mode that can be used to reduce power consumption when the devices are not in use.

In addition, the MAX9240GTM+T devices feature built-in adaptive equalization which compensates for signal degradation due to trace length and other factors. The adaptive equalization helps ensure that the signal passes through HDMI and SFF-8437 cable systems without signal loss.

Additionally, the MAX9240GTM+T devices feature an integrated clock data recovery (CDR) circuit that eliminates the need for an additional CDR. The integrated CDR provides jitter performance meeting or exceeding SFF-8437 specifications while providing more than double the jitter tolerance of typical CDR products.

The MAX9240GTM+T also provides adjustable de-emphasis to adjust the input signal amplitude, as well as integrated signal integrity features that reduce user design complexity. The signal pre-emphasis compensates for signal degradation due to trace length and other factors, and the signal integrity check feature verifies that the transmitted and received data are in sync.

The MAX9240GTM+T devices also feature built-in power sequencing and control. The integrated power control circuitry eliminates the need for an external voltage regulator, allowing for a more reliable, power-efficient design.

The MAX9240GTM+T have a high level of integration, providing a small form factor and low power consumption for applications requiring high-speed data transmission and reception across relatively short traces. The integrated clock and data recovery (CDR) circuit eliminates the need for an additional CDR and provides jitter performance meeting or exceeding SFF-8437 specifications. The integrated fanout buffer ensures e•cient mapping of lane, port, and side information. The adaptive equalization compensates for signal degradation due to trace length and other factors, while the signal pre-emphasis enables improved signal integrity with simpler designs, and power sequencing and control eliminates the need for an external voltage regulator. All of these features allow for more reliable and power-efficient designs.

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