MAX96709GTG+

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The MAX96709GTG+ is a high-performance universal serializer/deserializer (SERDES) architecture designed for high-speed serial communications. It is suitable for applications up to 10.3125Gbps, such as 10G/25G/50G/100G optical modules, and networks such as USB4.0, PCIe4.0, HDMI2.1, SAS4.0, SGPIO, 26G SFP+/QSFP28, CXP and CEI-11G standards. Based on the advanced chip fusion technology of the MAX9679, it not only integrates the serializer and deserializer, but also has the dual-channel configuration capability to improve the limit rate of the system. It enables two independent high-speed serial channels with separate reference clock inputs. The MAX96709GTG+ has a low jitter clock synthesizer to ensure excellent signal integrity. The low power consumption and the low latency architecture can realize the excellent performance for 10.3125 Gbps serial applications. The serializing and deserializing are processed in a fixed 10.3125Gbps data rate. When operating at lower rates, the architecture has the serializer and deserializer blocks to re-calibrate the transfer unit to effectively support higher intermediate data rates.The MAX96709GTG+ architecture includes an external reference clock receiver on the reference clock pin and a fractional-N PLL synthesizer. The receiver tolerates various clock accuracy specifications and provides very low jitter outputs to feed the serializer and deserializer blocks. The reference clock is digital data synchronized with the external reference clock and does not require any request/response or embedded address transfer protocols. The MAX96709GTG+ architecture uses low jitter, digital multi-phase PLLs that enable accurate frequency tuning over a wide range of operating frequencies. The architecture uses a low jitter, digital voltage-controlled oscillator (VCO) to drive the serializer and deserializer blocks. The fractional-N synthesizer achieves excellent overclocking capability and performance at the lowest jitter data rates and highest intermediation data rates.The MAX96709GTG+ architecture can transmit and receive data/control signals through external data transfer channels, allowing the architecture to be used as a universal SERDES. The architecture includes a differential receiver and transmitter that support differential input and output.The MAX96709GTG+ architecture eliminates the need for external IF circuits, making this architecture suitable for cost-sensitive applications and small form factors. The architecture also provides enhanced configurability and testability, and the ability to operate at a low power state.In conclusion, the MAX96709GTG+ is a high-performance universal serializer/deserializer architecture ideal for 10.3125Gbps applications. It features a low jitter clock synthesizer, low power consumption and low latency architecture, as well as an external reference clock receiver, fractional-N PLL synthesizer, low jitter, digital multi-phase PLLs, and voltage controlled oscillator. The architecture also offers enhanced configurability and testability with the ability to operate at low power states, eliminating the need for external IF circuits for cost-sensitive applications.

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