| Allicdata Part #: | MC100E151FNR2-ND |
| Manufacturer Part#: |
MC100E151FNR2 |
| Price: | $ 0.00 |
| Product Category: | Integrated Circuits (ICs) |
| Manufacturer: | ON Semiconductor |
| Short Description: | IC FF D-TYPE SNGL 6BIT 28PLCC |
| More Detail: | N/A |
| DataSheet: | MC100E151FNR2 Datasheet/PDF |
| Quantity: | 1000 |
| 1 +: | 0.00000 |
| Max Propagation Delay @ V, Max CL: | -- |
| Base Part Number: | 100E151 |
| Package / Case: | 28-LCC (J-Lead) |
| Mounting Type: | Surface Mount |
| Operating Temperature: | 0°C ~ 85°C (TA) |
| Current - Quiescent (Iq): | 78mA |
| Voltage - Supply: | -4.2 V ~ -5.7 V |
| Current - Output High, Low: | -- |
| Trigger Type: | Positive Edge |
| Series: | 100E |
| Clock Frequency: | 1.1GHz |
| Number of Bits per Element: | 6 |
| Number of Elements: | 1 |
| Output Type: | Differential |
| Type: | D-Type |
| Function: | Master Reset |
| Part Status: | Obsolete |
| Packaging: | Tape & Reel (TR) |
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The MC100E151FNR2 is a high speed two-input positive edge-trigged flip-flop with asynchronous reset and synchronous set. It has a wide range of applications, such as synchronous counters, registers, and other logic circuits.
The MC100E151FNR2 has a balanced-master-slave design which serves to latch data asynchronously after the rising edge of the clock pulse. The inputs of the flip-flop are the data inputs D, a clock input C, a reset input R and a set input S. The data input D is applied to the data-master input of the flip-flop, and is the data that is to be latched onto the Q output. The clock input CP is the edge-triggered clock. The reset input R and the set input S are active-low asynchronous control inputs. When the reset input is low, the flip-flop is forced to reset, causing the Q and complement Q outputs to be in the low state. When the set input is low, the flip-flop is forced to set, causing the Q and complement Q outputs to be in the high state.
When CP rises and R and S are both high, the data-master is clocked and the state of the data input presented to the data-master is latched onto the Q and complement Q outputs of the flip-flop. A low on either the reset or the set at any time forces the flip-flop into the reset or set states, independent of the state of the clock and data inputs at that time. This ensures that the outputs of the flip-flop always follow the asynchronous reset and set inputs even without a clock input transition.
The MC100E151FNR2 is especially useful in synchronous counters, registers, and other logic circuits since the data is not transferred until after the rising edge of the clock pulse. This ensures that the data is reliably transferred from one stage to the next, with no possibility of data glitches. It is also useful for applications in high speed data transfer, since the high speed operation ensures that the data is transferred quickly and without errors.
The MC100E151FNR2 is a high speed, dependable and economical flip-flop solution, and is suitable for all kinds of logic applications as well as low, medium and high speed data transfer applications. It is an ideal choice for logic circuit designs where reliable, fast operation, low power consumption and high speed are essential requirements.
The specific data is subject to PDF, and the above content is for reference
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MC100E151FNR2 Datasheet/PDF