
Allicdata Part #: | MC10EP101MNG-ND |
Manufacturer Part#: |
MC10EP101MNG |
Price: | $ 0.00 |
Product Category: | Integrated Circuits (ICs) |
Manufacturer: | ON Semiconductor |
Short Description: | IC GATE OR/NOR QUAD 4INP 32-QFN |
More Detail: | NOR/OR Gate Configurable 4 Circuit 16 Input (4, 4,... |
DataSheet: | ![]() |
Quantity: | 1000 |
1 +: | 0.00000 |
Series: | 10EP |
Packaging: | Tube |
Part Status: | Obsolete |
Logic Type: | NOR/OR Gate |
Number of Circuits: | 4 |
Number of Inputs: | 16 Input (4, 4, 4, 4) |
Schmitt Trigger Input: | No |
Output Type: | Differential |
Current - Output High, Low: | -- |
Voltage - Supply: | 3 V ~ 5.5 V |
Operating Temperature: | -40°C ~ 85°C |
Mounting Type: | Surface Mount |
Package / Case: | 32-VFQFN Exposed Pad |
Supplier Device Package: | 32-QFN (5x5) |
Base Part Number: | 10EP101 |
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The MC10EP101MNG is a multi-function, configurable, complementary metal–oxide–semiconductor (CMOS) device designed by ON Semiconductor to serve the logic-gates-and-inverters field. It integrates two high speed emitter coupled logic (ECL) inverters, two three-state TTL output buffers, two high speed low fan-out TTL output buffers, four logic Y-Gates and one data select circuit into one device. It is very versatile and able to replace multiple components on a circuit board, thereby simplifying circuit design.
The MC10EP101MNG operates at a power-supply voltage in a range of 5.0V to 11.4V. It has an operating temperature range of -55 to 125 °C. The maximum power consumption of the device is 5.5 mW. The maximum propagation delay of the ECL logic outputs is 8.3ns and the output enable time is 13.3ns. The rise and fall time of the TTL output buffers is >2ns.
The function of the MC10EP101MNG is determined by the settings of four control pins (A, B, C, and D). Each of the four pins is assigned specific control functions for the various logic gates and circuits. The settings determine the universality of the device.
The two ECL inverters, which are the heart of the MC10EP101MNG, receive their input from the two Y-Gates. Depending on their control settings, the four Y-Gates can be used as either a NAND (C = 0, D = 0) or a NOR (C = 1, D = 1) gate. The two TTL output buffers are controlled by an internal logic circuit, while the two high speed low fan-out TTL output buffers are controlled by separate control pins.
The data select circuit is activated when the BD control pin is tied to the high logic level and the C control pin is tied to the low logic level. The circuit takes signals from the two data inputs, D0 and D1, and passes the approperiate signal to certain outputs; D0 to DOUT1 and D1 to DOUT0. This allows for a great range of applications for the MC10EP101MNG.
The versatility of the MC10EP101MNG is why it is such a popular choice for logic-gates-and-inverters applications. It can replace multiple components while providing high speed, low power operation. The four control pins greatly increase the universality of the device, making it capable of a wide range of applications. This is why the MC10EP101MNG is a trusted choice for the logic-gates-and-inverters field.
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