TPS92518HVPWPT

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1. Describe

The TPS92518HVPWPT family of devices are dual buck devices LED current controller with SPI communication interface. Serial communication interface Provides a single communication path Multi-Channel and Platform Lighting Driver Modules (LDM) application. TPS92518 uses quasi-hysteretic control Methods to support switching frequency range From 1 kHz to 2 MHz. This control method enables Excellent high frequency shunt FET dimming, also Handling adaptive demanding dynamic loads LED matrix based headlamp system. Software programmable SPI set point (accuracy Peak Current, Controlled Off-Time and Output voltage detection) enables designers to develop a single LED Driver Solutions for Multiple Load Configurations Can be quickly reconfigured for future LED drivers Design requirements. The TPS92518 device has an input range up to 42V. The TPS92518HV is a high voltage option with Input range up to 65 V.

2. Feature

    1. Wide input voltage range of 6.5 V to 65 V

    2. Two independent buck LED controllers

        – High bandwidth, quasi-hysteretic control

        – Adjustable high-end sensing

        – Direct PWM dimming input

        – Cycle-by-cycle current limit

    3. SPI communication interface

        – Software configurable set point (8 bits)

        – Digital calibration and binning

        – Fault monitoring and reporting

    4. Advanced high precision dimming

        – 10,000:1 PWM dimming range

        – 255:1 analog dimming range

        – High frequency shunt FET dimming

3. Application

    1. Color mixing application

    2. Aftermarket lighting applications

    3. LED general lighting

    4. Projector application

4. Pin configuration

5. Pin Description

6. Function Description

The TPS92518 operates using peak current, constant off-time control. Two states determine the high-side FET control. The switch opens and remains open until the set peak current is reached. The peak current is controlled by monitoring the voltage across the sense resistor. The peak current is reached when the voltage drop is above the programming threshold. The switch is then closed, initiating a shutdown cycle. The internal capacitor is then charged by the current source, which is related to the VLEDx pin voltage. The off-time ends when the capacitor voltage reaches the threshold controlled by the DAC. The off-time capacitor resets and the main switch opens to begin the next on-cycle.

7. Constant Off-Time and Constant µs×V Operation

Although commonly referred to as constant off-time, the off-time does vary with the output voltage in the standard TPS92518 configuration. This relationship ensures constant peak-to-peak inductor current ripple (ΔIL-PP). Although uncommon, the VLEDx pins can be set to a fixed value to produce a truly constant off-time and limit the frequency of change, but with reduced current regulation. To maintain regulation and constant ripple voltage across the various outputs, the converter off-time must be shorter or longer as the VLEDx pin voltage changes. This results in a change in frequency. In this regard, the off-time register can be thought of as a second-by-volt setting (s × V) for the converter. The TPS92518 Electrical Characteristics table specification for off-time specifies the duration of a certain off-time for a certain register value. This time also depends on the VLEDx pin voltage. For example, for VVLEDx= 30 V and LEDx_TOFF_DAC = 255, the off-time is specified as 4 µs. Internal analog circuit Operates to keep the product of ripple and µs V (microsecond volts) constant. If the LEDx voltage changes to 15 V, the off time is adjusted to 8 µs. If the LEDx voltage becomes 60 V, the off time is adjusted to 2 µs, and so on.

8. OFF Timer

The converter Off-time is controlled via the LEDx_TOFF_DAC[7:0] register and VLEDx pin. The VLEDx pin voltage is converted to a current that charges an internal capacitor to a voltage set by the LEDx_TOFF_DAC creating a delay. Details of this circuit are shown in the Functional Block Diagram. Deriving the off-time from the output voltage creates a ramp representing the inductor current. When the TPS92518 is first enabled (All UVLO levels are cleared) both timer capacitor pull-downs are disabled allowing voltage to increase on the internal timer capacitors. When either capacitor reaches the matching DAC control voltage, the high-side FET is turned on, starting a switching cycle. The maximum off-time timer is always dominant at start-up when the output is completely discharged or when shunt FET dimming and the shunt FET shunts the output for the required period.