72V3624L15PF

Bus Directional:	Bi-Directional
Base Part Number:	72V3624
Supplier Device Package:	128-TQFP (14x20)
Package / Case:	128-LQFP
Mounting Type:	Surface Mount
Operating Temperature:	0°C ~ 70°C
FWFT Support:	Yes
Retransmit Capability:	No
Programmable Flags Support:	Yes
Expansion Type:	Width
Series:	72V
Current - Supply (Max):	400mA
Voltage - Supply:	3V ~ 3.6V
Access Time:	10ns
Data Rate:	66.7MHz
Function:	Synchronous
Memory Size:	18K (256 x 36 x 2)
Part Status:	Obsolete
Packaging:	Tray

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Logic - FIFOs Memory : 72V3624L15PF Application Field and Working PrincipleFIFOs memory, also known as First-In/First-Out memory, is a type of logical memory that follow the principle of ‘first in, first out’ while preserving the original ordering of data entering the memory. FIFOs are widely used to bridge two systems with asynchronous data transfer speeds, because of its capability to store data and match the speeds of two different systems. The 72V3624L15PF is a FIFOs type of logic memory device developed by Texas Instruments. It features banks of memory organization and increased speed capability.DescriptionThe 72V3624L15PF is a FIFOs device with a 15-bit by 255-word register organization. It is a fully programmable device that is well-suited for applications that require data transfer between two asynchronous systems operating at different speeds. It operates at speeds up to 72Mbit/s and is capable of handling data transfers of up to 15 bits. It is also a non-volatile memory which is ideal for producing a long-term memory backup. The 72V3624L15PF operates from a 6.5 to 3.3V single power supply with bypass decoupling. It is pin-compatible with its lower speed counterpart, the 72V3622L.Application FieldThe 72V3624L15PF is designed for a variety of data transfer applications including between two processors, communication links, A/D and D/A conversion, and general-purpose data buffering. It is ideal for applications that require transferring data between multiple devices. Its ability to handle data transfer of up to 15 bits makes it suitable for use in applications such as embedded systems, digital signal processing, robotics, and telecommunications.Working PrincipleThe 72V3624L15PF is composed of two memory blocks - an input FIFO and an output FIFO. The input FIFO stores data in a serial fashion, while the output FIFO stores data in a parallel fashion. Data is transferred between the two blocks according to the ‘first in, first out’ principle. When data is written into the input FIFO, it is shifted out in the same order. When data is written into the output FIFO, it is shifted out in the same order.The device also features a user-programmable priority selection. The priority selection allows data to be transferred between the two FIFOs according to a predetermined priority. It also features programmable word formats, including standard and byte-oriented.The 72V3624L15PF also features a programmable partial word width mode which allows the data stored in the memory blocks to be in variable word lengths. This feature is useful for applications that require data with variable word widths, such as speech and audio applications.In addition, the 72V3624L15PF has a programmable loop-back mode which allows data to be looped back from the output FIFO to the input FIFO. The loop-back mode is useful for applications such as video and image processing, which require real-time processing of data.ConclusionThe 72V3624L15PF is a FIFOs type of logic memory device developed by Texas Instruments. It features banks of memory organization and increased speed capability. It operates at speeds up to 72Mbit/s and is capable of handling data transfers of up to 15 bits. It is designed for a variety of data transfer applications including between two processors, communication links, A/D and D/A conversion, and general-purpose data buffering. Its user-programmable priority selection allows data to be transferred between the two FIFOs according to a predetermined priority, while its programmable partial word width mode allows the data stored in the memory blocks to be in variable word lengths. The device also features a programmable loop-back mode which allows data to be looped back from the output FIFO to the input FIFO.

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