74LVC373AD,118 Allicdata Electronics
Allicdata Part #:

1727-6681-2-ND

Manufacturer Part#:

74LVC373AD,118

Price: $ 0.14
Product Category:

Integrated Circuits (ICs)

Manufacturer: Nexperia USA Inc.
Short Description: IC OCTAL D TRANSP LATCH 20SOIC
More Detail: D-Type Transparent Latch 1 Channel 8:8 IC Tri-Stat...
DataSheet: 74LVC373AD,118 datasheet74LVC373AD,118 Datasheet/PDF
Quantity: 1000
2000 +: $ 0.12890
6000 +: $ 0.12058
10000 +: $ 0.11227
50000 +: $ 0.10395
Stock 1000Can Ship Immediately
$ 0.14
Specifications
Series: 74LVC
Packaging: Tape & Reel (TR) 
Part Status: Active
Logic Type: D-Type Transparent Latch
Circuit: 8:8
Output Type: Tri-State
Voltage - Supply: 2.7 V ~ 3.6 V
Independent Circuits: 1
Delay Time - Propagation: 1.5ns
Current - Output High, Low: 24mA, 24mA
Operating Temperature: -40°C ~ 125°C
Mounting Type: Surface Mount
Package / Case: 20-SOIC (0.295", 7.50mm Width)
Supplier Device Package: 20-SO
Base Part Number: 74LVC373
Description

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Logic - Latches

The 74LVC373AD,118 is a member of the low voltage CMOS family of logic devices. It is a type of latch, a circuit or device that can store one bit of information (binary state) over a period of time, and which is designed according to a specific logic level and operating characteristics. This type of latch, often referred to as an eight-bit latch, is designed to latch data information, primarily in memory applications.

Application Field

The 74LVC373AD,118 is typically used in volatile memory applications, such as read/write memory and programmable logic arrays (PLAs). It can also be used in nonvolatile memory applications, such as field programmable gate arrays (FPGAs), as well as in digital signal processing (DSP) and general purpose interface (GPI) applications. The latch is also often used to store data that is used to decode signals within a microcontroller or microprocessor.

Working Principle

The 74LVC373AD,118 latch operates on two distinct logic levels, the logic level 0 and logic level 1. When the latch is in logic level 0, the data stored within is defined as "off"; when the latch is in logic level 1, the data stored within is defined as "on". The latch can be activated in either logic level 0 or logic level 1 by applying a single-cycle pulse signal. This signal triggers the latch and changes its state from 0 or 1 to the opposite state. The pulse signal must have a clock frequency equal to or higher than the frequency of the signal to be latched.

The output of the latch is determined by the following equation:
Output = State + Cn + Cn+1

Where "State" stands for the data state of the latch, "Cn" stands for the clock n-bit, and "Cn+1" stands for the clock (n + 1)-bit. For the latch to be activated and the data state of the latch to be changed, both "Cn" and "Cn+1" must be logic 1. If either of them is logic 0, the latch will not be changed and the data state of the latch will remain the same.

The 74LVC373AD,118 latch has two types of input terminals, the "Set" and "Clear" pins. The Set pin, when brought high, will set the output of the latch to the logic 1 level, regardless of the state of the other input and output pins. The Clear pin, when brought high, will reset the output of the latch to logic 0 level.

The 74LVC373AD,118 latch also has a reset pin, which can be used to reset the latch and restore it to the logic 0 state. When the reset pin is brought low, it will reset the latch, regardless of the state of the other input and output pins.

In conclusion, the 74LVC373AD,118 latch is a type of latch designed for use in volatile and nonvolatile memory applications. It is designed to latch data information and is controlled by single-cycle pulse signals. The output of the latch is determined by the logic level of the clock leads as well as the data state of the latch. It also has input terminals for both Set and Clear functions which can be used to control the output of the latch. Lastly, the reset pin can be utilized to reset the latch back to its initial state.

The specific data is subject to PDF, and the above content is for reference

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