74LVC373ADTR2G

Series:	74LVC
Packaging:	Tape & Reel (TR)
Part Status:	Active
Logic Type:	D-Type Transparent Latch
Circuit:	8:8
Output Type:	Tri-State
Voltage - Supply:	1.2 V ~ 3.6 V
Independent Circuits:	1
Delay Time - Propagation:	1.5ns
Current - Output High, Low:	24mA, 24mA
Operating Temperature:	-40°C ~ 125°C
Mounting Type:	Surface Mount
Package / Case:	20-TSSOP (0.173", 4.40mm Width)
Supplier Device Package:	20-TSSOP

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Logic - Latches

74LVC373ADTR2G is a low power, high performance, low voltage logic latch.

The 74LVC373ADTR2G is a 3-state, octal, edge-triggered latch designed to interface with low voltage/low power logic systems. The device is designed such that the input levels are compatible with both TTL and CMOS level logic systems. It is used in applications where low noise and low power levels are desired.The device is composed of three main components: the latch, the enable, and the tri-state combination output buffer. The latch is an electronic device that stores one bit of data. When enabled, the latch captures the input ONCE until the enable is disabled or a RESET signal is received. The enable feature allows the user to control when the data is latched and when it is not. The tri-state combination output buffer allows the user to control the output of the device hence allowing the output signals to receive different logic levels.The primary application fields of the 74LVC373ADTR2G are memory devices, bus systems, computing, and communication applications. Its high performance level can be beneficial when used in high speed data communication and processor functions. Specifically, the device is suitable for applications which require rapid address latching and data latching.The working principle of the device is very simple. When the enable signal of the latch is pulled high, the data that was previously stored can be outputted at this time. During this, the device will remain in a constant state as long as the enable remains high. Now, if we want to update the data, the latch must first be disabled by pulling the enable low and then set to the new data. Once the data has been set, the enable can be pulled high again for the device to output the updated data.The device comprises of an octal latch, each of which consists of two internal stages: an edge-triggered positive edge-triggered latch, and a negative edge-detector. The positive edge-triggered latch works such that it outputs the data at the positive-going edge of the enable. The negative edge-detector ensures that the data is also outputted at the negative-going edge of the enable thus allowing for continual data transfer even when the enable is low. The output buffer has three states: active high, active low and high-impedance (HI-Z). The active high and active low states are used to select between two different output levels when the enable is high. Additionally, the HI-Z state is used to output a logic 0 when the enable is low. The combination of these states allows the user to tailor the output to the desired logic level.In conclusion, the 74LVC373ADTR2G is a low power, high performance, low voltage logic latch. It has many applications in memory, bus systems, computing and communication systems. The device comprises of an octal latch, enable and the tri-state combination output buffer. The working principle of the device is simple; when enabled, the data is latched and when disabled, the data can be set. The combination of these features makes the 74LVC373ADTR2G an ideal choice for applications which require high speed data communication and processor functions.

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