74LVC573APW,118 Integrated Circuits (ICs) |
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Allicdata Part #: | 1727-3077-2-ND |
Manufacturer Part#: |
74LVC573APW,118 |
Price: | $ 0.10 |
Product Category: | Integrated Circuits (ICs) |
Manufacturer: | Nexperia USA Inc. |
Short Description: | IC OCTAL TRANSPAR LATCH 20-TSSOP |
More Detail: | D-Type Transparent Latch 1 Channel 8:8 IC Tri-Stat... |
DataSheet: | 74LVC573APW,118 Datasheet/PDF |
Quantity: | 2500 |
2500 +: | $ 0.08700 |
5000 +: | $ 0.08174 |
12500 +: | $ 0.07646 |
25000 +: | $ 0.07013 |
62500 +: | $ 0.06750 |
Series: | 74LVC |
Packaging: | Tape & Reel (TR) |
Part Status: | Active |
Logic Type: | D-Type Transparent Latch |
Circuit: | 8:8 |
Output Type: | Tri-State |
Voltage - Supply: | 1.2 V ~ 3.6 V |
Independent Circuits: | 1 |
Delay Time - Propagation: | 1.5ns |
Current - Output High, Low: | 24mA, 24mA |
Operating Temperature: | -40°C ~ 125°C |
Mounting Type: | Surface Mount |
Package / Case: | 20-TSSOP (0.173", 4.40mm Width) |
Supplier Device Package: | 20-TSSOP |
Base Part Number: | 74LVC573 |
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The 74LVC573APW,118 is a Logic – Latch device. It is a single 5 V supply Octal D-Type Flip Flop with 3-State Outputs. The 74LVC573APW,118 has two separate 8-bit output ‘D’ type registers that are controlled by the Chip Enable (1CE) and Output Enable (1OE) inputs from the application. It is especially suitable for high-speed bipolar memory applications.
The term ‘Latch’ is used to describe a Flip Flop with additional control inputs. In the case of the 74LVC573APW,118, the inputs are the Chip Enable (1CE) and Output Enable (1OE) inputs. These allow the data on the data bus to be written into the Register, but also allow the output data to be sent to the output buffer or the ‘3-State’ enabling logic so that the output data can be either driven or tri-stated.
The 74LVC573APW,118 consists of two separate 8-bit output registers, each connected to a two-input data bus. The data bus for each register allows for two 8-bit words to be simultaneously transferred into the register. When the data enters the register, the register will take the incoming data as the new data value and the data on the output terminals will be the same as the new data.
The 74LVC573APW,118 has two control inputs, Chip Enable (1CE) and Output Enable (1OE). When the 1CE input is high, data on the data bus is written into the register that corresponds to the 1CE input. When the 1OE pin is high, the data stored in the registers will be driven to the output buffer, and the output will be in the same state as the data stored in the registers. The 74LVC573APW,118 also has a ‘3-state’ control pin which will tri-state the output buffer when active. This gives the ability to selectively disable the outputs in order to reduce the loading on the output devices and improve system timing characteristics.
The 74LVC573APW,118 is a latch device that is ideal for high-speed bipolar memory applications. Its two separate 8-bit output registers can receive data simultaneously and store it until the 1OE is pulsed high, driving the stored data to the output register. The 3-state control pin allows selective control of the outputs, making it a great choice for applications where operations must be performed quickly, but system loading needs to be kept to a minimum.
The specific data is subject to PDF, and the above content is for reference
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