85102AGILF

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Clock/timing signals are a vital part of any digital system and are often key to the system\'s operational stability and reliability. Clock/timing signals are used to synchronize data transfer, as well as provide timing or clocking in order to control operations or interactions between functional blocks of a system. A variety of principles are employed to generate clock/timing signals. Most commonly, these are produced from oscillators, such as a crystal oscillator or voltage controlled oscillator (VCO) and associated frequency divider circuits.

When distributing a clock/timing signal to different parts of a system, the signal must be broadcast such that the signal remains stable and timing skew is minimized. This requires that the amplitude, rise and fall times and phase differences of the output signal be maintained. A buffer is used in order to protect the source of the clock signal from noise, glitches and loading effects, while increasing the ability of the signal to be distributed. A buffer will receive an input signal, invert it and drive the output with a specified amount of gain and slew rate.

The 85102AGILF is a low-jitter, low power, 6:1 clock/timing buffer/fanout device with integrated phase selection. The device is used for the generation and distribution of high-performance clocks for the main system and its I/O control. It contains six identical differential clock buffers providing the same differential outputs from one differential reference clock-input. The 85102AGILF offers low propagation time skew between its output clocks, low jitter and low power consumption.

The main benefit of the 85102AGILF is that it is ideal for timing and synchronization applications that require multiple, absolute-phase-accurate copies of the same clock at high speeds. It offers 6 buffered copies of the original input clock and allows the user to select different output clocks with predetermined, absolute phase differences. This is ideal when synchronizing two parts of a system which require different, absolute-phase accurate clock signals and eliminates the need for additional circuits, saving cost and space.

The 85102AGILF is configured using a simple digital selection pin. It is divided into two sections: the first section, comprising of three buffers, with predefined phase output of 45, 90 and 135 °; and the second section containing three more buffer outputs with predefined phase shift of 225, 270 and 315°. All outputs are synchronized with the common input frequency. The second section enables the user to select up to two output clocks with predetermined, absolute phase differences of 180°.

The device can support data rates of up to 400 Mbps, making it suitable for applications such as Gigabit Ethernet, Fibre Channel and SerDes links. It also features very low glitch and cycle-to-cycle jitter, as well as very low power consumption. These features make it ideal for jitter-sensitive applications, such as PCIe or similar protocol. Furthermore, the device is available in an industry-standard SSOP16 package, which simplifies circuit layout and allows it to be used in a wide range of systems.

The 85102AGILF is a very useful device for generating high-performance clocks. By providing 6 buffered copies of the same clock signal with different, absolute phased output and extremely low jitter and power consumption, the 85102AGILF keeps the system operating in total synchrony, creating more stable and reliable systems.

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