| Allicdata Part #: | 800-3245-ND |
| Manufacturer Part#: |
85210AY-31LF |
| Price: | $ 0.00 |
| Product Category: | Integrated Circuits (ICs) |
| Manufacturer: | IDT, Integrated Device Technology Inc |
| Short Description: | IC CLK BUFFER 1:5 650MHZ 32TQFP |
| More Detail: | Clock Fanout Buffer (Distribution) IC 1:5 650MHz 3... |
| DataSheet: | 85210AY-31LF Datasheet/PDF |
| Quantity: | 1000 |
| 1 +: | 0.00000 |
| Series: | -- |
| Packaging: | Tray |
| Part Status: | Obsolete |
| Type: | Fanout Buffer (Distribution) |
| Number of Circuits: | 2 |
| Ratio - Input:Output: | 1:5 |
| Differential - Input:Output: | Yes/Yes |
| Input: | HCSL, LVDS, LVHSTL, LVPECL, SSTL |
| Output: | HSTL |
| Frequency - Max: | 650MHz |
| Voltage - Supply: | 3.135 V ~ 3.465 V |
| Operating Temperature: | 0°C ~ 70°C |
| Mounting Type: | Surface Mount |
| Package / Case: | 32-LQFP |
| Supplier Device Package: | 32-TQFP (7x7) |
| Base Part Number: | ICS85210-31 |
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The 85210AY-31LF is a versatile, high-performance CMOS clock buffer ideal for many different applications. It can be used in high performance timing applications such as bus clock dividers, memory controllers, and multi-ddress backup power sources. It can also be used in low-voltage applications such as TTL, ECL and SERDES clock buffers and common-mode termination circuits.
The 85210AY-31LF employs three state logic to selectively buffer or terminate inputs. All outputs are user-programmable and may be individually configured as push-pull or three state outputs. The 85210AY-31LF also features a low on-resistance, wide signal range and low output skew.
The 85210AY-31LF is a differential buffer employing three state logic to terminate the signal inputs. The inputs can be positive and negative logic, for push-pull or three state outputs. The 85210AY-31LF contains a clock divider, two differential pulse receivers, and two differential pulse drivers. The clock dividers divide the input clock signal into two separate clock signals, one at the frequency of the input clock, and one at half the frequency of the input clock. The pulse receivers are used to detect the edges of the clock signal, while the pulse drivers generate the desired output clocks. There are two outputs, A and B and they can be used to drive push-pull outputs or three-state outputs.
The 85210AY-31LF is designed for use in high performance timing applications such as bus clocks dividers, memory controllers and multi-address backups. It features low on-resistance, wide signal range and low output skews, making it ideal for such applications. It is suitable for use as a low voltage TTL, ECL and SERDES clock buffer, and can serve as a common mode termination circuit. With its low power requirements, small size and programmable outputs, it is a great device for applications needing a reliable clock signal.
The 85210AY-31LF is one of the most versatile clock buffers currently available. It is suitable for a broad range of applications and can be used for many different tasks. With its low power requirements, wide signal range, low output skew and three state logic, it is an invaluable tool for high performance timing applications such as bus clock dividers and memory controllers. It can also be used in low voltage applications such as TTL, ECL and SERDES clock buffers, and even serve as a common mode termination circuit.
The specific data is subject to PDF, and the above content is for reference
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85210AY-31LF Datasheet/PDF