Allicdata Part #: | 9112AM-17LFT-ND |
Manufacturer Part#: |
9112AM-17LFT |
Price: | $ 1.72 |
Product Category: | Integrated Circuits (ICs) |
Manufacturer: | IDT, Integrated Device Technology Inc |
Short Description: | IC BUFFER HI PERFORMANCE 16-SOIC |
More Detail: | N/A |
DataSheet: | 9112AM-17LFT Datasheet/PDF |
Quantity: | 1000 |
2500 +: | $ 1.55849 |
Differential - Input:Output: | No/No |
Base Part Number: | ICS9112-17 |
Supplier Device Package: | 16-SOIC |
Package / Case: | 16-SOIC (0.154", 3.90mm Width) |
Mounting Type: | Surface Mount |
Operating Temperature: | 0°C ~ 70°C |
Voltage - Supply: | 2.97 V ~ 5.5 V |
Divider/Multiplier: | No/No |
Frequency - Max: | 133MHz |
Series: | -- |
Ratio - Input:Output: | 1:9 |
Number of Circuits: | 1 |
Output: | Clock |
Input: | Clock |
PLL: | Yes with Bypass |
Type: | Zero Delay Buffer |
Part Status: | Last Time Buy |
Packaging: | Tape & Reel (TR) |
Due to market price fluctuations, if you need to purchase or consult the price. You can contact us or emial to us: sales@allicdata.com
The 9112AM-17LFT is a member of the TXCO family of products from Microchip, and it is designed to provide highly accurate and low-power time base signals for applications such as clock and datacom systems, precision measurement and control systems, and timing and synchronization systems. The device offers a versatile, low-power solution for regulating frequency and offers a wide frequency range of up to 150 MHz. The device is ideal for applications requiring cost-effective time base signals in a small form factor.
The 9112AM-17LFT is a 3-channel clock generator that provides two differential clock outputs and one CASC (Controlled Advancement of Start Clocking) output. The clock generator contains an oscillator, a crystal, a programmable frequency filter, and a logic circuit that provides a reference frequency. The 9112AM-17LFT can produce a wide range of frequencies from 7.8 kHz to 150 MHz. The device is capable of generating precise, low-jitter clock signals with a typical jitter of 40-45 fs. The clock generator is able to accurately produce up to 80 frequency settings via internal crystal parameter values.
The 9112AM-17LFT uses an Advanced Clock-Phased Locked Loop (PLL) architecture to generate a reference frequency for its output clock signals. This architecture ensures low jitter and frequency deviation. The PLL architecture also provides flexibility in complying with frequency modulation requirements. The 9112AM-17LFT can be used in both phase locked and non-phase locked mode to generate clock signals with precise frequency control.
The 9112AM-17LFT can be controlled via its external crystal oscillator input or an external logic signal. The external logic signals can be used to advance or retard the reference frequency of the output clock signals, which in turn, controls the phase delay of the output clock signals. The device also supports programmable user-defined frequency settings that can be adjusted via the external crystal oscillator input. The frequency filter allows the user to fine-tune the frequency of the output clock signals.
In addition to its frequency control capabilities, the 9112AM-17LFT also offers several features designed to reduce current draw. These features include an adjustable low-power input buffer, an ultra-low power detection circuit, programmable logic outputs, and a low-power wake-up signal. All of these features work together to reduce current draw and power consumption while allowing for precise control of the clock signals.
In summary, the 9112AM-17LFT is an ideal choice for applications requiring precise and cost-effective time base signals in a small form factor. Its advanced PLL architecture and low-power design make it a great choice for applications requiring precise frequency control and low power consumption. Whether used in phase-locked or non-phase-locked mode, the 9112AM-17LFT provides an ideal solution for clock and datacom systems, precision measurement and control systems, and timing and synchronization systems.
The specific data is subject to PDF, and the above content is for reference
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