954204CGLFT

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954204CGLFT – Application Specific and Working Principle

954204CGLFT, also known as “Gb/s N-PLL high performance fractional-N synthesizer”, is a clock/timing application specific component. It is a low power, high performance, and low jitter synthesizer working on the principle of Fractional-N Synthesis – a modified version of the Phase-Locked Loop (PLL) optimized mainly to provide improved clock accuracy and eliminate jitter.

The main application field of this component is in the high-end communications and computing industry. It is mainly used to generate clocks and enable switching within high-performance systems requiring tight synchronization. In this sense, it is extremely useful in systems such as DDR and PCIe applications and it has been used in a wide range of additional systems such as Gigabit Ethernet, DWDM, SONET/SDH, broadcast, radio, and many others.

The working principle of 954204CGLFT consists of three major blocks: a fractional-N synthesizer, a voltage controlled oscillator, and a frequency divider. The fractional-N synthesizer, which is based on PLL, is used to divide the oscillator output frequency with a dynamically adjustable integer and fractional divide ratio.

The fractional-N synthesizer block is composed of four basic components: a reference divider, a digital PLL loop, a voltage controlled oscillator, and a frequency divider. The reference divider divides a reference frequency by a integer programmable divide ratio. This divided signal is fed to the second block, which is the digital PLL loop, which compares the frequency of the divided reference signal with the feedback signal from the VCO. If the frequencies differ, the PLL loop will correct the difference. This corrective action is determined by a digital loop filter.

The third block, the VCO, works on the principle of generating an output frequency that is proportional to the voltage applied. It is the fundamental frequency source of the 954204CGLFT and it is regulated by the PLL loop through the corrective action determined by the digital loop filter.

The fourth block, the frequency divider, is used to divide down the output frequency of the VCO by a programmable integer value. It is used to obtain an output frequency of the synthesizer that is within the specific frequency range required. The output of the frequency divider is fed to the PLL loop to be compared again with the reference frequency to ensure accuracy.

The main advantage of this component is that it consumes low power and provides very low jitter; as low as 2ps, which is approximately 50% less than conventional PLL synthesizers. Additionally, it offers a fractional-N design with a programmable base frequency, as well as a wide range of multiplication ratio and divisions, resulting in precision system performance.

In summary, 954204CGLFT is a clock/timing specific component used in a wide range of applications requiring high-precision synchronization. The fractional-N synthesizer, composed of the three basic blocks of reference divider, digital PLL loop, and VCO, works by correcting the differences in frequency between the input and the output signal. Its advantage is that it consumes low power and provides very low jitter, making it a high performance and low cost solution.

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