BU7331EKN-E2

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Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers

BU7331EKN-E2 clock generator is a high performance, small footprint and cost-effective solution for industrial communication, networking, and wireless-/wireless communication system applications. BU7331EKN-E2 provides precise and accurate generation and reception of clock signals, allowing functions such as counter timing and precise clock acquisition/transmission.

Application Field

BU7331EKN-E2 design target is aimed at the world industrial communication, telecommunications, and wireless communication markets. It can be used in a wide range of fields, including:

• Industrial communication buses, such as CAN Bus, Sercos Bus, PROFIBUS, and Fieldbus.
• Telecommunication line cards
• VoIP telephony
• Wireless infrastructure
• Data/storage networking
• Wireless-/wireless networking
• High-precision timing control
• Test & Measurement applications

Working Principle

BU7331EKN-E2 clock generator works at the precision timing of buffered clock signals. It generates precise output clock signals whose frequency depends on the reference clock. This is possible because BU7331EKN-E2 integrates two components: a digitally programmable PLL and an equally programmable Fractional-N synthesis core.

This combination enables fine adjustment of output frequencies, with minimal jitter, even when the reference clock source has significant noise and drift.

The clock generator normally runs in two modes - Slave mode and Generate mode. In Slave mode, it locks on to the reference clock and generates a stable clock output of a fixed frequency. In Generate mode, it autonomously generates a stable clock output at a frequency determined by a programmable frequency register.

The BU7331EKN-E2 are designed to ensure an extremely low phase jitter. Jitter is an important consideration when designing high-speed circuits, as it can introduce noise and disturb signal integrity. The jitter performance can be further improved by selecting an appropriate loop filter for the PLL.

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