CC1021RSSR

Working Principle

CC1021RSSR operates using a two-stage architecture. The first stage is the transmitter, which converts the digital signal into an RF signal by using the modulation scheme and encodes the signal into a bitstream. The bitstream is then sent through the antenna to reach the receiver. The receiver then decodes the bitstream and the signal is handed to the receiver for further processing.

The transmitter of the CC1021RSSR is with an integrated frequency synthesizer. This allows the transceiver to create a variety of RF signals from the same base signal. Additionally, the integrated frequency synthesizer enables the transmission of data over multiple channels. This can be beneficial in areas with higher interference levels or limited available bandwidth.

The receiver of the CC1021RSSR is with an integrated low-IF mixer. This allows the receiver to reduce the image noise and maximize sensitivity of the receiver. The receiver also includes a selectable clock source which allows the selection of an external clock to reduce noise. The receiver also includes a low-noise voltage regulator which improves the performance of the system and reduces power dissipation.

The CC1021RSSR also includes high-efficiency PA, DC supply, and RX DC bias for improving the overall system performance. Additionally, the CC1021RSSR includes an integrated low-noise amplifier which reduces noise and improves the receiver performance. Moreover, the CC1021RSSR has many additional features such as an integrated RTC, UART interface, and SPI port which can be used to communicate with the host processor.