Allicdata Part #: | 296-16758-2-ND |
Manufacturer Part#: |
CDCU877GQLT |
Price: | $ 0.00 |
Product Category: | Integrated Circuits (ICs) |
Manufacturer: | Texas Instruments |
Short Description: | IC PLL CLOCK DRIVER 1.8V 52-BGA |
More Detail: | N/A |
DataSheet: | CDCU877GQLT Datasheet/PDF |
Quantity: | 1000 |
Ratio - Input:Output: | 1:10 |
Base Part Number: | CDCU877 |
Supplier Device Package: | 56-BGA MICROSTAR JUNIOR (7.0x4.5) |
Package / Case: | 56-VFBGA |
Mounting Type: | Surface Mount |
Operating Temperature: | -40°C ~ 85°C |
Voltage - Supply: | 1.7 V ~ 1.9 V |
Frequency - Max: | 400MHz |
Differential - Input:Output: | Yes/Yes |
Series: | -- |
Number of Circuits: | 1 |
Output: | SSTL-18 |
Input: | SSTL-18 |
Main Purpose: | Memory, DDR2 |
PLL: | Yes |
Part Status: | Not For New Designs |
Packaging: | Tape & Reel (TR) |
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CDCU877GQLT is a high performance single-chip clock and data recovery device. The device operates up to 650MHz serial data link over a wide range of temperature conditions and is ideal for applications requiring high jitter tolerance. This device supports both clock and data recovery functions and covers a wide range of frequencies and data rates.
CDCU877GQLT is designed for use in clock/timing applications specific to Automotive and Industrial markets. It offers a number of features that make it suitable for demanding clock/timing applications, including a single-ended output drive, high-quality phase-locked loop (PLL), low phase noise on the output clock, and a wide range of adjustable phase-locked-loop (PLL) parameters.
CDCU877GQLT utilizes multi-level data compression technique (MLDC) to achieve superior signal integrity and jitter tolerance. The device allows data rates up to 650MHz and is resistant to changes in ambient temperature and supply voltage. The device is also available in a variety of Pb-Free packages and is RoHS-compliant.
CDCU877GQLT consists of an analog phase locked loop (PLL) and a data recovery circuit. The PLL consists of a variable frequency oscillator (VFO) with a well-defined phase for obtaining stable control of the output clock and data. The data recovery circuit consists of a clock-data separator, jitter filter and decoder. The clock-data separator extracts the output clock frequency, while the jitter filter removes undesirable peakiness of the signal, and the decoder extracts the output data.
The PLL has two control modes, manual and automatic. In manual mode, the resonant frequency is generated by an active control loop. This mode can be used in applications where the output frequency is stable over a wide temperature range. In the automatic mode, the resonant frequency is determined by an automatic gain control (AGC) loop. This mode can be used to achieve better frequency control when operating over a varying temperature range.
CDCU877GQLT also offers an adjustable spread-spectrum clock (SSC) feature that is used to spread the output clocks on multiple frequencies. This feature is used to reduce possible radio-frequency interference (RFI). It is also designed for simple integration with digital logic to produce a single-ended output waveform. A digital delay control is implemented, which helps minimize system board area and simplifies board level layout.
The CDCU877GQLT is a low-power clock and data recovery device that is ideal for Automotive and Industrial clock and timing applications. It provides a robust clock/data recovery solution that is resistant to changes in ambient temperature, supply voltage and jitter. It is a design-friendly device with a high level of integration, making it a cost-effective solution for demanding clock/timing control applications.
The specific data is subject to PDF, and the above content is for reference
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