DRV8301QDCAQ1

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1. Description

The DRV8301QDCAQ1 device is an automotive gate driver IC for three phase motor drive applications. The device provides three half bridge drivers, each capable of driving two N-type MOSFETs, one for the high-side and one for the low side. The device supports up to 2.3-A sink and 1.7-A source peak current capability and only needs a single power supply with a wide range from 6 to 60 V. The DRV8301-Q1 device uses bootstrap gate drivers with trickle charge circuitry to support 100% duty cycle. The gate driver uses automatic hand shaking when high-side FET or low-side FET is switching to prevent current shoot through. VDS of FETs is sensed to protect external power stage during overcurrent conditions. The DRV8301-Q1 device includes two current shunt amplifiers for accurate current measurement. The current amplifiers support bi-directional current sensing and provide an adjustable output offset of up to 3 V. The DRV8301-Q1 device also has an integrated switching mode buck converter with adjustable output and switching frequency to support MCU or additional system power needs. The buck is capable to drive up to 1.5-A load. The SPI interface provides detailed fault reporting and flexible parameter settings such as gain options for current shunt amplifier, slew rate control of gate driver, and other settings.

2. Features

    1. Qualified for Automotive Applications

    2. AEC-Q100 Tested With the Following Results:

        – Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range

        – Device HBM ESD Classification Level 2

        – Device CDM ESD Classification Level C4A

    3. Operating Supply Voltage 6 to 60 V

    4. 2.3-A Sink and 1.7-A Source Gate Drive Current Capability

    5. Integrated Dual Shunt Current Amplifiers With Adjustable Gain and Offset

    6. Integrated Buck Converter to Support up to 1.5-A External Load

    7. Independent Control of 3 or 6 PWM Inputs 

    8. Bootstrap Gate Driver With 100% Duty Cycle Support

    9. Programmable Dead Time to Protect External FETs from Shoot-Through

  10. Slew Rate Control for EMI Reduction

  11. Programmable Overcurrent Protection of External MOSFETs

  12. Support Both 3.3-V and 5-V Digital Interface

  13. SPI Interface

  14. Thermally Enhanced 56-Pin HTSSOP Pad-Down DCA Package

3. Applications

    1. Automotive 3-Phase Brushless DC Motor and Permanent Magnet Synchronous Motor

    2. Water, Oil, Fuel Pumps

4. Pin configuration

5. Three-Phase Gate Driver

The half-bridge drivers use a bootstrap configuration with a trickle charge pump to support 100% duty cycle operation. Each half-bridge is configured to drive two N-channel MOSFETs, one for the high-side and one for the low-side. The half-bridge drivers can be used in combination to drive a 3-phase motor or separately to drive various other loads. The peak gate drive current and internal dead times are adjustable to accommodate a variety of external MOSFETs and applications. The peak gate drive current is set through a register setting and the dead time is adjusted with an external resistor on the DTC pin. Shorting the DTC pin to ground will provide the minimum dead time (50 ns). There is an internal hand shake between the high side and low side MOSFETs during switching transitions to prevent current shoot through. The three-phase gate driver can provide up to 30 mA of average gate drive current. This will support switching frequencies up to 200 kHz when the MOSFET Qg = 25 nC. Each MOSFET gate driver has a VDS sensing circuit for overcurrent protection. The sense circuit measures the voltage from the drain to the source of the external MOSFETs while the MOSFET is enabled. This voltage is compared against the programmed trip point to determine if an overcurrent event has occurred. The high-side sense is between the PVDD1 and SH_X pins. The low-side sense is between the SH_X and SL_X pins. Ensuring a differential, low impedance connection to the external MOSFETs for these lines will help provide accurate VDS sensing.

6. Current Shunt Amplifiers

The DRV8301QDCAQ1 includes two high-performance current shunt amplifiers to accurate low-side, inline current measurement. The current shunt amplifiers have four programmable GAIN settings through the SPI registers. These are 10, 20, 40, and 80 V/V. The current shunt amplifiers provide output offset up to 3 V to support bidirectional current sensing. The offset is set to half the voltage on the reference pin (REF). To minimize DC offset and drift overtemperature, a calibration method is provided through either the DC_CAL pin or SPI register. When DC calibration is enabled, the device will short the input of the current shunt amplifier and disconnect the load. DC calibration can be done at any time, even during MOSFET switching, because is disconnected. For the best results, perform the DC calibration during the switching OFF period, when no load is present, to reduce the potential noise impact to the amplifier.

7. Buck Converter

The DRV8301-Q1 uses an integrated TPS54160 1.5 A, 60 V, step-down DC-DC converter. Although integrated in the same device, the buck converter is designed completely independent of the rest of the gate driver circuitry. Because the buck converter will support external MCU or other external power need, the independency of buck operation is very critical for a reliable system; this will give the buck converter minimum impact from gate driver operations. Some examples are: when gate driver shuts down due to any failure, buck will still operate unless the fault is coming from buck itself. The buck keeps operating at much lower PVDD of 3.5 V, this will assure the system to have a smooth power-up and power-down sequence when gate driver is not able to operate due to a low PVDD.

8. Start-up and Shutdown Sequence Control

During power up all gate drive outputs are held low. Normal operation of gate driver and current shunt amplifiers can be initiated by toggling EN_GATE from a low state to a high state. If no errors are present, the DRV8301-Q1 is ready to accept PWM inputs. Gate driver always has control of the power FETs even in gate disable mode as long as PVDD is within functional region. There is an internal diode from SDO to VDD_SPI, so VDD_SPI is required to be powered to the same power level as other SPI devices (if there is any SDO signal from other devices) all the time. VDD_SPI supply should be powered up first before any signal appears at SDO pin and powered down after completing all communications at SDO pin.

9. Application Information

The DRV8301QDCAQ1 is a gate driver designed to drive a three-phase BLDC motor in conjunction with an external power MOSFET. The device is highly integrated with three half-bridge gate drivers, two current-shunt amplifiers, overcurrent protection, and a step-down buck regulator.