Allicdata Part #: | DS1086LU-12F/T&R-ND |
Manufacturer Part#: |
DS1086LU-12F/T&R |
Price: | $ 0.00 |
Product Category: | Integrated Circuits (ICs) |
Manufacturer: | Maxim Integrated |
Short Description: | IC ECONOSILLATOR 3.3V SS 8-USOP |
More Detail: | N/A |
DataSheet: | DS1086LU-12F/T&R Datasheet/PDF |
Quantity: | 1000 |
1 +: | 0.00000 |
Differential - Input:Output: | No/No |
Base Part Number: | DS1086L |
Supplier Device Package: | 8-uMAX |
Package / Case: | 8-TSSOP, 8-MSOP (0.118", 3.00mm Width) |
Mounting Type: | Surface Mount |
Operating Temperature: | -40°C ~ 85°C |
Voltage - Supply: | 2.7 V ~ 3.6 V |
Divider/Multiplier: | Yes/No |
Frequency - Max: | 66.6MHz |
Series: | EconOscillator™ |
Ratio - Input:Output: | 1:1 |
Number of Circuits: | 1 |
Output: | Clock |
Input: | Clock |
PLL: | No |
Type: | Spread Spectrum Clock Generator |
Part Status: | Obsolete |
Packaging: | Tape & Reel (TR) |
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The DS1086LU-12F/T&R is a versatile clock generator in the Clock/Timing –Clock Generators, PLLs and Frequency Synthesizers category. With this device, it is easy for designers to generate single output, low jitter and low noise clock frequencies from a single low frequency reference signal.
This device is an integrated IC solution, available in a small 8-Pin SOIC (Small Outline IC) package and operates from a wide 1.9 to 5.5 V supply. It employs PLL circuitry to generate multiple low frequency reference outputs and programmable frequency synthesizers. The DS1086LU-12F/T&R can generate frequencies ranging from 8.192 to 113.188 MHz.
The device implements a dual output low frequency oscillator section and utilizes a PLL with a voltage controlled oscillator (VCXO) along with integrated fractional-N and integer-N frequency synthesizer core to generate high frequency clocks. The device is compatible with industry standard low frequency references such as ECL and LVCMOS. It is also compatible with various low frequency source reference clock frequencies, including 10 MHz and 25 MHz.
Regarding its application field, the default and best performance for the device is in broadcast and video applications. It enables and supports the video encoder and video decoding requirements such as 3D video, HD 720p and 1080i video; as well as audio signal generation in digital video broadcast TV. Moreover, the flexibility of the device supports the multiple reference clock inputs from low frequency sources, making it ideal for a wide range of applications such as audio signal synthesis in digital radio broadcast and HD radio broadcast, digital signal processor (DSP) based designs, IP and VoIP communications, digital cable TV, CATV, and digital satellite TV systems.
The working principle of the device is simple but very effective. First, it extracts the reference clocks from the internal oscillator of the device, and then produces a synthesized output with very low jitter. This is done by the integrated PLL and frequency synthesizer. The output clocks have very low jitter which is beneficial when used in system designs and applications where clock jitter should be minimized. The device also features programmable outputs, allowing the user to select either a low jitter or a stretchable low frequency output.
The device is also capable of using multiple reference clocks. This can be done by either using two separate reference clocks or combining two or more clocks and synthesizing the output frequency simultaneously. In addition, the device can be programmed to generate five different output frequency ranges from 2-100 megahertz, enabling designers to generate the exact output frequency desired for their applications.
The DS1086LU-12F/T&R is an ideal solution for a wide range of industries and applications. This integrated IC features a wide range of frequency synthesis, high clock jitter reduction, versatile output frequency options, and multiple reference clock inputs. With this device, designers can easily generate single output, low jitter, and low noise clock frequencies from a single low frequency reference.
The specific data is subject to PDF, and the above content is for reference
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