EPM2210F256I5N

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1. Describe

MAX® II family of instant-on, nonvolatile CPLDs based on a 0.18 µm, 6-layer Metal Flash process with densities of 240 to 2,210 logic elements (LEs) (128 to 2,210 equivalent macrocells) and 8 Kbits of nonvolatile sexual storage. Compared with other CPLD architectures, MAX II devices provide high I/O count, fast performance, and reliable adaptability. Features a MultiVolt core, user flash memory (UFM) blocks, and Enhanced In-System Programmability (ISP), MAX II devices are designed to reduce cost and power while providing programmable solution .

2. Feature

    1. Low cost, low power CPLD

    2. Instant-on, non-volatile architecture

    3. Standby current as low as 25 µA

    4. Provides fast propagation delay and clock-to-output time

    5. Provides four global clocks, two available per logic array block (LAB)

    6. UFM blocks up to 8 Kbits for non-volatile storage

    7. MultiVolt core provides 3.3 V/2.5 V or 1.8 V external supply voltage for the device

    8. MultiVolt I/O interface supports 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels

    9. Bus-friendly architecture including programmable slew rate, drive strength, bus hold and programmable pull-up resistors

  10. Schmitt trigger supports noise margin input (programmable per pin)

  11. I/Os are fully compliant with the Peripheral Component Interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification for 3.3-V operation at 66 MHz

  12. Support hot swap

  13. Built-in Joint Test Action Group (JTAG) Boundary Scan Test (BST) circuitry compliant with IEEE standards. 1149.1-1990

  14. The ISP circuit complies with IEEE standards. 1532