ISL81486IU

The ISL81486IU, manufactured by Intersil, is an IC that provides a power-on reset solution with a push-pull or open-drain output. The device has a quality threshold detector and two low-voltage reset outputs. The quality threshold detector is designed to monitor a VDD voltage level with respect to an independent and programmable threshold level. It provides an indication of power-on reset (POR) and power-good (PG) to an externally connected microprocessor or other logic circuits.

Applications:

• Power-on reset / Power-good controller with pre-charge time delay for ICs, such as microprocessors, FPGAs, ASICs, and DSPs.
• Intelligent power supervisor and reset controller.
• Power supply start-up supervisor.
• Pre-bias start-up control and supervisor.

Working Principle:

The ISL81486IU has an internal low-voltage reset (LVR) generator with two outputs. When VDD voltage rises above the unique threshold, VSEN rises, the outputs of the Quality Threshold Detector (QTD) become high logic level, and the reset outputs are held low until the supply voltage rises above the internal reset voltage (VH) and the output of the POR delay block reaches the internal LVR comparator level.

When the supply voltage rises above VH, the outputs of both QTD latch and delay block latch are set to “1.” At this time, the POR and PG signals will become high after the delay time, tDELAY. When both the POR and PG signals reach the high logic level, the internal reset pre-charge is starting.

The supply voltage must reach a higher voltage VH2 for a certain period of time (tPC) to satisfy the reset pre-charge condition before asserting the low logic level signals. After the reset pre-charge is satisfied, the reset outputs will be down to the low logic level and the reset pulse signals are generated. Both POR and PG output signals will also go back low.

The QTD of the device is designed to keep two unique thresholds, VT and VSEN, in order to monitor the supply voltage. The high logic level of the QTD output indicates that the VDD voltage is higher than the threshold. The VSEN threshold is dependent on the internal temperature, which allows the device to maintain a low level reset voltage over temperature.

The device has an internal timer designed to provide a reset pulse width with respect to the on-chip supply voltage. The reset time-out can be set up as short as 0.5 ms for VSEN threshold and the wide range starting from 0.4 ms up to 10 seconds for VT threshold.