ISO7221ADR Allicdata Electronics

ISO7221ADR Isolators

Allicdata Part #:

296-21955-2-ND

Manufacturer Part#:

ISO7221ADR

Price: $ 1.20
Product Category:

Isolators

Manufacturer: Texas Instruments
Short Description: DGTL ISO 2.5KV GEN PURP 8SOICGeneral Purpose Digit...
More Detail: N/A
DataSheet: ISO7221ADR datasheetISO7221ADR Datasheet/PDF
Quantity: 20000
1 +: $ 1.20000
10 +: $ 1.16400
100 +: $ 1.14000
1000 +: $ 1.11600
10000 +: $ 1.08000
Stock 20000Can Ship Immediately
$ 1.2
Specifications
Series: --
Packaging: Tape & Reel (TR) 
Part Status: Active
Technology: Capacitive Coupling
Type: General Purpose
Isolated Power: No
Number of Channels: 2
Inputs - Side 1/Side 2: 1/1
Channel Type: Unidirectional
Voltage - Isolation: 2500Vrms
Common Mode Transient Immunity (Min): 25kV/µs
Data Rate: 1Mbps
Propagation Delay tpLH / tpHL (Max): 475ns, 475ns
Pulse Width Distortion (Max): 14ns
Rise / Fall Time (Typ): 1ns, 1ns
Voltage - Supply: 3 V ~ 5.5 V
Operating Temperature: -40°C ~ 125°C
Mounting Type: Surface Mount
Package / Case: 8-SOIC (0.154", 3.90mm Width)
Supplier Device Package: 8-SOIC
Base Part Number: --
Description

1. Description

ISO7221ADR series devices are dual-channel digital isolators. To facilitate PCB layout, the channels are in the same direction during installation.

The opposite direction in ISO7221ADR.

These devices have logical input and output buffers Silicon dioxide by TI (SiO2) Isolation Barrier, providing galvanic isolation up to 4000 VPK Every VDE. Use with isolated power supply Power supply, these devices can block high voltage and isolate Ground, and prevent noise current on the data Bus or other circuit enters local ground And interfere with or damage sensitive circuits.

The binary input signal is adjusted and converted to Balance the signal and then differentiate it through the capacitor Isolation barrier. Across the isolation barrier, Differential comparator receive logic conversion Information, then set or reset the trigger, and The output circuit is corresponding. The periodic update pulse is Go through obstacles to ensure proper DC level Output. If this DC refresh pulse is not received Every 4μs, assuming that the input is not powered on or Not actively driven, and fail-safe circuits Drive the output to a logic high state.

Small capacitance and the resulting time constant Provide fast operation with available signal rate From 0 Mbps (DC) to 150 Mbps ( A line means The transmission rate per second, in bps). Aoption, B-option and C-option devices have TTL Input threshold and noise filter at the input Prevent transient pulses from passing to The output of the device. M option device has CMOS VCC/2 input threshold, and there is no Input noise filter and additional propagation delay.

ISO7221ADR device Need two 2.8 V (C level), 3.3 V power supply voltage,5 V, or any combination. All inputs are 5V withstand voltage When powered by 2.8V or 3.3V power supply The output is 4 mA CMOS.

ISO7221ADR device is Suitable for environmental conditions Temperature range from –40°C to +125°C

2. Features

    1. 1, 5, 25 and 150 Mbps signaling rate options

         -Low output skew between channels; Max 1ns

         -Low pulse width distortion (PWD); maximum 1ns

         -Low jitter content; 1 ns typical at 150 Mbps

    2. 50 kV/μs typical transient immunity

    3. Operate at 2.8V (C level),3.3V or 5V power supply

    4. 4kV ESD protection

    5. High electromagnetic immunity

    6. –40°C to +125°C operating range

    7. Typical life of 28 years under rated voltage

    8. Safety related certification

         –VDE basic insulation with 4000-VPK VIOTM, 560 VPK VIORM according to DIN VDE V 0884-11: 2017-01 And DIN EN 61010-1 (VDE 0411-1)

         -2500 VRMS isolation according to UL 1577

         – CSA approved for use in IEC 60950-1 and IEC 62368-1

3. Application field

    1. Industrial Fieldbus

        – Modbus

        – Profibus™

        – DeviceNet™ data bus

    2. Computer peripheral interface

    3. Servo control interface

    4. data collection

4. Pin Configuration and Functions

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5. Functional Block Diagram

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6. PACKAGE OUTLINE

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