Allicdata Part #: | LE9531DMQC-ND |
Manufacturer Part#: |
LE9531DMQC |
Price: | $ 0.00 |
Product Category: | Integrated Circuits (ICs) |
Manufacturer: | Microsemi Corporation |
Short Description: | IC SLIC 1CH UNIV 145V 28QFN |
More Detail: | Telecom IC Subscriber Line Interface Concept (SLIC... |
DataSheet: | LE9531DMQC Datasheet/PDF |
Quantity: | 1000 |
1 +: | 0.00000 |
Series: | -- |
Packaging: | -- |
Part Status: | Obsolete |
Function: | Subscriber Line Interface Concept (SLIC) |
Interface: | Parallel |
Number of Circuits: | 1 |
Voltage - Supply: | 3.3V |
Current - Supply: | 40mA |
Operating Temperature: | -- |
Mounting Type: | -- |
Package / Case: | -- |
Supplier Device Package: | -- |
Includes: | -- |
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LE9531DMQC Application Field and Working Principle
The LE9531DMQC is a silicon-based integrated circuit (IC) designed for use in High-speed differential input transceiver and clock/data recovery applications. It is designed for use in mixed-signal, industrial and consumer electronics applications. Specifically, it is ideal for cellular, DSL, and other wireline and wireless communications systems requiring High Speed Data Transmission up to 10Gbps.
The LE9531DMQC is based on a wide-band differential input transceiver chipset and incorporates logic level translation between the high-speed differential data stream and low-voltage logic. The transceiver operates over a wide temperature range (-40 to +85ºC) and is capable of transmitting 10Gbps data over a cable length of 50m.
The transceiver is built around a high-speed differential input and output (IDO) receiver and an output buffer, providing a total electrical isolation between the high-speed and low-voltage-logic (LVL) I/Os. The receiver provides an input sensitivity of 1V dual differential with a maximum data rate of 10Gbps (1G-S/S).
The device is also equipped with a clock/data recovery (CDR) module which uses a phase-locked loop (PLL) to extract a clock signal from the received data stream. The PLL is capable of recovering the transmitted clock in both amplitude and phase variations. The output of the CDR circuit is buffered and low-noise. For added flexibility, the device also has a de-skew function which can be used to synchronize the clock to the data stream.
The transceiver\'s output is generated by a low-noise, high-bandwidth output buffer which amplifies the differential data, thus ensuring low power consumption and error-free data transmission over long distances. The low voltage I/Os of the device (VCCL and GND) provide direct connection to the LVL bus of the system.
In summary, the LE9531DMQC provides a flexible solution for High Speed Data Transmission up to 10Gbps and is suitable for a variety of industrial and consumer electronics applications. It offers excellent performance over temperature, is low power yet high speed, and is a highly integrated solution that requires minimal external components.
The specific data is subject to PDF, and the above content is for reference
Part Number | Manufacturer | Price | Quantity | Description |
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LE9531DMQCT | Microsemi Co... | 0.0 $ | 1000 | IC SLIC 1CH UNIV 145V 28Q... |
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LE9500CBJCT | Microsemi Co... | -- | 1000 | IC SLIC 1CH UNIV 10V 28PL... |
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LE9520SDDTC | Microsemi Co... | 0.0 $ | 1000 | IC SLIC 1CH UNIV 145V 64T... |
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LE9531CETC | Microsemi Co... | -- | 1000 | IC SLIC 1CH UNIV 100V 48T... |
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LE9531DMQC | Microsemi Co... | 0.0 $ | 1000 | IC SLIC 1CH UNIV 145V 28Q... |
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