| Allicdata Part #: | LTC6957IDD-2#TRPBF-ND |
| Manufacturer Part#: |
LTC6957IDD-2#TRPBF |
| Price: | $ 3.16 |
| Product Category: | Integrated Circuits (ICs) |
| Manufacturer: | Linear Technology/Analog Devices |
| Short Description: | IC CLK BUFFER DVR 1:2 12DFN |
| More Detail: | Clock Fanout Buffer (Distribution) IC 1:2 300MHz 1... |
| DataSheet: | LTC6957IDD-2#TRPBF Datasheet/PDF |
| Quantity: | 1000 |
| 2500 +: | $ 2.87244 |
| Series: | -- |
| Packaging: | Tape & Reel (TR) |
| Part Status: | Active |
| Type: | Fanout Buffer (Distribution) |
| Number of Circuits: | 1 |
| Ratio - Input:Output: | 1:2 |
| Differential - Input:Output: | Yes/Yes |
| Input: | CML, CMOS, LVDS, LVPECL |
| Output: | LVDS |
| Frequency - Max: | 300MHz |
| Voltage - Supply: | 3.15 V ~ 3.45 V |
| Operating Temperature: | -40°C ~ 85°C |
| Mounting Type: | Surface Mount |
| Package / Case: | 12-WFDFN Exposed Pad |
| Supplier Device Package: | 12-DFN (3x3) |
| Base Part Number: | LTC6957 |
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Clock/Timing is a major component of the entire communication and computing infrastructure, it is necessary to ensure that all parts of the system are synchronized. The LTC6957IDD-2#TRPBF is a high performance, low phase noise clock distribution IC used in a wide range of applications that require well-defined clock division, low jitter and skew, frequency insurance and proper fan out.
The LTC6957IDD-2#TRPBF is a differential-input, differential-output programmable PLL clock distribution IC. It is a single-supply, 2.5V to 5.5V device that integrates a low noise PLL, skew management, temperature-compensated current steering DAC, and an 8-phase output clock driver. The integrated PLL can be used with clock signals from 10MHz to 400MHz.
The LTC6957IDD-2#TRPBF provides up to 4 channels of programmable or fixed-value clock frequencies for each of the 8 differential outputs. It also features a programmable output enable and/or sync signal that can be used to control other clock ICs, such as receivers, transceivers, and peripheral controllers. Clock Division: The LTC6957IDD-2#TRPBF can divide down any input clock frequency to any of the 8 output frequencies. This is accomplished by writing the appropriate frequency division ratio to the device\'s internal phase accumulator.
The programmable phase-locked loop (PLL) inside the LTC6957IDD-2#TRPBF circuit is used to maintain an accurate output frequency, no matter what the input frequency is. The PLL also ensures low jitter and low phase noise for clock frequencies below 300MHz. Output Skew Management: The LTC6957IDD-2#TRPBF includes a fine-tune skew control that is used to equalize the output of each channel. This is accomplished by writing a divider coefficient to one of the output register, thus compensating for the delay of that output.
The LTC6957IDD-2#TRPBF includes an integrated temperature-compensated current steering DAC and a fast-switch CMOS output driver that can drive up to 1.2mA at each differential output. This ensures that each output is driven with low distortion and acceptable levels of noise, even when driving large loads. Frequency Insurance: The LTC6957IDD-2#TRPBF can be used to ensure that the output frequency remains within an acceptable range, even when the input frequency varies by up to 50%. This is accomplished by using a Frequency Insurance feature.
The Frequency Insurance feature monitors the input frequency and automatically adjusts the output frequency when it goes out of the specified range. The frequency range, along with a margin, can be configured through the SPI interface. Programmable Output Enable and Sync Signal: The LTC6957IDD-2#TRPBF can be used to drive other clock ICs, such as receivers, transceivers, and peripheral controllers. This is accomplished by writing a programmable enable (or sync) signal to one of the output registers, thus enabling or disabling the output.
In summary, the LTC6957IDD-2#TRPBF is a high performance, low phase noise clock distribution IC used in a wide range of applications that require well-defined clock division, low jitter and skew, frequency insurance and proper fan out. It includes an integrated PLL and skew management to maintain an accurate output frequency, no matter what the input frequency is, and a temperature-compensated current steering DAC and a fast-switch CMOS output driver to drive each output with low distortion and acceptable levels of noise. The programmable output enable and/or sync signals can be used to control other clock ICs, such as receivers, transceivers, and peripheral controllers.
The specific data is subject to PDF, and the above content is for reference
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LTC6957IDD-2#TRPBF Datasheet/PDF