M2006-02-622.0800

Series:	--
Packaging:	Tray
Part Status:	Obsolete
PLL:	Yes
Input:	LVDS, LVPECL
Output:	LVPECL
Number of Circuits:	1
Ratio - Input:Output:	2:2
Differential - Input:Output:	Yes/Yes
Frequency - Max:	622.08MHz
Divider/Multiplier:	Yes/No
Voltage - Supply:	3.135 V ~ 3.465 V
Operating Temperature:	0°C ~ 70°C
Mounting Type:	Surface Mount
Package / Case:	36-CLCC
Supplier Device Package:	36-CLCC

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M2006-02-622.0800
Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers The M2006-02-622.0800 is a logic IC (integrated circuit) designed and manufactured by Mitsubishi Electric Corporation. It is a dual 16-bit phase and frequency synthesizer IC that can generate simultaneously two outputs of closely matching square waveform signals in sync. It is designed to generate and produce a variety of signals ranging from single frequency signals in the very low frequency range, such as frequencies used in electronic watches and clocks, to signals of complex patterns and higher frequencies. This IC is ideal for use in applications such as automotive, telecom and test equipment, and any other applications where the generation of complex and closely matched clock signals is desired. The M2006-02-622.0800 is designed to provide a versatile means of generating and producing variety of signals, both single frequency and multiple, to meet the timing requirements of a wide range of applications. Using an internal Phase-Locked Loop (PLL) and a digitally implemented prescaler circuit, the PLL can be configured to accept an input clock of up to 10MHz and generate one, two or even more synchronized square wave outputs at any frequency up to 10MHz. The two output signals are matched in frequency and symmetry to 4 parts per million (ppm), satisfying the Signal-to-Noise Ratio (SNR) requirements of demanding applications such as automotive electronics and telecom security. The design of the M2006-02-622.0800 was based on the concept of having an internal PLL that utilizes a digitally implemented pre-scaler circuit. The pre-scaler circuit is designed to accept an input clock of up to 10MHz and generate a set of loop signals that will form the basis of the PLL loop. The PLL circuit then uses these loop signals as the basis for generating one, two or more output signals that match in terms of frequency and symmetry to 4ppm. The end result is that the frequency of the output signals can be programmed to approximately any value up to 10MHz, with the only limitation being the accuracy of the input clock frequency. The M2006-02-622.0800 utilizes Mitsubishi’s unique DFG logic technology to achieve high speed and low jitter operation. This technology enables the PLL to achieve a guaranteed cycle resolution of 10 MHz/1048576, and also allows other features to be included such as programmable startup delay and data initialization. Additional programmability options such as waveform shaping and frequency dividers are also integrated in the M2006-02-622.0800, allowing easy and flexible configurations. One of the most attractive features of this IC is its low power consumption, with a maximum operating current of only 10mA. In summary, the M2006-02-622.0800 is an ideal IC for frequency synthesis applications requiring two synchronized square wave outputs with 4ppm matching. Its versatility in producing wide variety of signals, from low frequencies used in digital watches and clocks, to higher frequencies required in automotive and telecom applications, and its low power consumption make it a highly desirable IC for high-precision clock and timing applications.

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