MAX9310EUP+

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The MAX9310EUP+ is a low-skew, high-frequency, three-state buffer designed to take a single-ended clock signal, invert it if desired, and drive one to eight differential outputs without violating skew specifications. This part is suitable for applications requiring signal synchronization, signal distribution and PLL or DLL clocktree building. It is ideal for driving low-voltage differential signaling (LVDS) and small-outline dual in-line memory module (SODIMM) memories.

The MAX9310EUP+ operates from a single +3.3V supply and is available in 16-pin SOIC and 16-pin TSSOP packages. The low-skew buffering of the MAX9310EUP+ is advantageous for clock tree applications where multiple signals must be routed and synchronized at the same speed. The chip also supports applications that require multiple copies of the same data independent of the actual data content.

Features:

• Buffer Delays: 35ps (typ)
• Data Rate: 200MHz (min)
• Input Voltage Range: VCC-0.3V to VCC+0.3V
• Propagation Delay: 175ps (max)
• Differential-to-Differential Skew: 2ps (max)
• Output-to-Output Skew: 2ps (max)
• Transmission Delay: 175ps (max)
• Input Clock Rise/Fall Time: 3 ns (max) for 2.5V, 7 ns (max) for 1.5V

Application field:

• PowerPC SlimPort & SOV
• LVTTL to LVDS Buffers
• SerDes Buffer amplifiers
• PCI Express Root Complexes and Endpoints
• Clock Management ICs
• FPGAs and ASICs
• Backplanes, Optocouplers, and High-Speed Fans
• Mobile Multimedia Devices
• Ethernet/Fiber Channel/ SATA Networking
• Netbus, USB, and PATA
• Switch Fabric Networking
• Data Communications
  

Working Principle:

The MAX9310EUP+ buffer is a differential signal amplifier that takes in one differential input clock signal (IN+, IN-), and outputs one to eight differential clock signals (OUT+, OUT-). The circuit also provides options for clock inversion and booster drive circuits for low-voltage paring (LVP).

The circuit is designed to amplify the differential input signal to the inverted signal, then drive the signal out to eight differential terminal pairs (OUT+ to OUT-, OUT1 to OUT1…). The part also contains the necessary logic to drive the three-state outputs when the logic low level is applied to the three-state inputs, which shuts off the outputs from damaged output stages. The MAX9310EUP+ buffers can drive up to +400mA in unloaded conditions allowing the devices to drive both high-fanout devices as well as bus terminators.

The MAX9310EUP+ is designed with flexibility in mind, allowing it to be used in 5V and 3.3V systems when connecting to VL-terminated bus transceivers. It also incorporates slew rate control which reduces undesirable ground bounce, an issue that can arise in applications with many active differential outputs.

The MAX9310EUP+ device also provides adjustable output-to-output skew control, allowing the user to control skew more accurately while still operating within the specified specifications. The adjustable output-to-output skew feature improves accuracy and timing margins, an important feature if multiple clocks must be used in a system.

The MAX9310EUP+ helps to reduce system cost and complexity, as it is typically much easier to drive one to eight differential outputs from one buffer than from multiple small-package chips. The device also has ultra-low jitter, making it suitable for high-speed systems.

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