| Allicdata Part #: | MC14517BDWR2-ND |
| Manufacturer Part#: |
MC14517BDWR2 |
| Price: | $ 0.00 |
| Product Category: | Integrated Circuits (ICs) |
| Manufacturer: | ON Semiconductor |
| Short Description: | IC SHIFT REG DUAL 64BIT 16-SOIC |
| More Detail: | N/A |
| DataSheet: |  MC14517BDWR2 Datasheet/PDF |
| Quantity: | 1000 |
| 1 +: | 0.00000 |
Specifications
| Series: | 4000B |
| Packaging: | Tape & Reel (TR) |
| Part Status: | Obsolete |
| Logic Type: | Shift Register |
| Output Type: | Tri-State |
| Number of Elements: | 2 |
| Number of Bits per Element: | 64 |
| Function: | Serial to Parallel |
| Voltage - Supply: | 3 V ~ 18 V |
| Operating Temperature: | -55°C ~ 125°C |
| Mounting Type: | Surface Mount |
| Package / Case: | 16-SOIC (0.295", 7.50mm Width) |
| Supplier Device Package: | 16-SOIC |
| Base Part Number: | 4517 |
Description
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The MC14517BDWR2 is a high-performance CMOS 8-bit serial-to-parallel shift register. It is capable of operating with wide ranges of voltage so it is suitable for many applications. Constructed with silicon-gate CMOS technology, it offers very low-power operation and high noise immunity due its superior high-impedance input/output logic levels.This device is well-suited for shift register and recirculator applications, which require a sparsely populated parallel-output format. In shift register mode, data is presented on the serial input A with each clock transition (CLK) shifting the data one bit toward the parallel-output port. By generating the appropriate number of clock pulses at the clock input (CLK), the A input data can be shifted into the eight parallel-outputs.In recirculator applications, data can be circulated back to the serial inputs of the device upon reaching the parallel-outputs. The data is clocked into the register from serial-input A and leaves at serial-output B. The serial inputs and outputs are in complementary forms so that data can be applied on either side for recirculation purposes.The device is equipped with an asynchronous clear (CLR) and an asynchronous parallel-load (PL) input. The clear and load inputs determine whether data present on the parallel-inputs will be loaded into the device or when the device will be cleared and reset to a logic LOW level.The MC14517BDWR2 provides appropriate logic levels to ensure compatibility with data-bus applications. The inverse of each output appears as the complement of that output, providing a signal that is the true inverse of its complement.In summary, the MC14517BDWR2 is a versatile 8-bit shift register which can be applied to a myriad of applications. It features low power consumption and high noise immunity, along with a wide range of input/output logic levels to enable compatibility with data-bus applications. Furthermore, it is equipped with an asynchronous clear and parallel-load input that enable greater flexibility and control over data entry.
The specific data is subject to PDF, and the above content is for reference
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