PL613-51QC-R

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PL613-51QC-R (hereinafter referred to as PL613-51QC-R) is a clock generator, PLLs, and frequency synthesizers. It is designed to provide a reliable and easy to use single-chip source of source clocks. PL613-51QC-R features a high performance, low power, differential PLL that enables the generation of extremely stable and highly accurate frequency outputs in a variety of fields.

Application Field

PL613-51QC-R can apply in a variety of applications, such as telecommunications, networking, consumer electronics, digital video, etc. It is suitable for reference clock source and clock synthesis in base station applications, MRO/LTE systems and digital video systems. The PL613-51QC-R can also be used in data communication systems such as Ethernet, Serial ATA, SAS, and SD-WAN. This device is also suitable for other clock sources in consumer audio/video and mobile applications.

Working Principle

The PL613-51QC-R works by using a differential PLL design, enabling a high linearity and low noise structure with a 1.6-GHz input frequency, allowing for a wide range of configurations to provide ultra-low jitter output. This device is capable of achieving up to 10MHz jitter values. The frequency accuracy of the device can be as low as +/-1ppm. The differential input provides protection against EMI and reduces leakage current, extending the lifetime of the device.

The PLL architecture employed by PL613-51QC-R allows two outputs; one follows the input clock frequency with a configurable Fractional-N divider or Integer-N prescaler, while the other can produce a frequency up to 150MHz with a wide calibration range that ensures a reliable output reference clock. The device also supports programming of the start value, stop value and step size to accommodate arbitrary frequencies.

Additionally, the PL613-51QC-R features integrated low-noise oscillator for optimal jitter performance at the output. The oscillator includes an adjustable load capacitor can be tuned to optimize any frequency range. This removes the need for an external clocksource. The device also includes a crystal-locking interface for low-noise crystal oscillators, providing a reliable and ultra-low-jitter reference clock in an industry-standard 8MHz crystal footprint.

The PL613-51QC-R also supports single-sided sensing, with a programmable hysteresis level. This eliminates the need to sense both clock edges, providing a more cost effective solution with only one phase detector.

Conclusion

The PL613-51QC-R is a single-chip solution for low-noise clock generation, jitter performance, and wide frequency range applications. It supports an extensive range of features, such as a fractional-N divider, an adjustable load capacitor, an integrated crystal-locking interface, and programmable hysteresis levels, providing a reliable and low-cost solution for clock source and clock synthesis applications.

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