PL686-35OC

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The PL686-35OC is a high performance differential clock fanout buffer. It converts a single-ended input clock signal into eight LVECL or eight differential CML outputs. This device is designed to distribute low jitter clocks in numerous application markets, such as telecom, datacom, high-end consumer, storage, and computing. The PL686-35OC is optimized to be used in multiple clocking systems that require multiple low skew outputs from a single input.

A typical application field of the PL686-35OC is clock fanout for synchronous systems. It offers a fanout rate of 1/8 with reduced jitter, input-to-output skew, and transmission delay. The PL686-35OC is CMOS compatible and operates from a single +3.3V power supply voltage at a maximum frequency of 600MHz. It is also able to support fine adjustment and low phase noise.

The working principle of the PL686-35OC is relatively simple. When an input clock signal is applied to the device, it is amplified and converted into eight LVECL or eight differential CML outputs. The circuit contains an internal phase-locked loop (PLL) and an analog delay line, which are used to condition and adjust the input clock signal and output clock signals respectively. The analog delay line is used to compensate the clock skews between the input clock signal and the output clock signals, while the PLL is used to eliminate any jitter and phase noise from the output clock signals.

The PL686-35OC also incorporates an on-chip inhibit function, which is used to disable a group of output clock signals. This is particularly useful in applications where the system must be synchronized to one clock source. It also features integrated power-on reset (POR) and test-mode pins, which allow the user to select the output frequencies, enable/disable the outputs and test the device. All these features make the PL686-35OC a versatile and reliable clock fanout for multiple clocking systems.

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