Allicdata Part #: | PL902166USY-ND |
Manufacturer Part#: |
PL902166USY |
Price: | $ 2.23 |
Product Category: | Integrated Circuits (ICs) |
Manufacturer: | Microchip Technology |
Short Description: | JITTER BLOCKER |
More Detail: | N/A |
DataSheet: | PL902166USY Datasheet/PDF |
Quantity: | 1000 |
200 +: | $ 2.02781 |
Series: | Jitter Blocker™ |
Packaging: | Cut Strip |
Part Status: | Active |
PLL: | No |
Input: | LVCMOS |
Output: | LVCMOS |
Number of Circuits: | 1 |
Ratio - Input:Output: | 1:2 |
Differential - Input:Output: | No/No |
Frequency - Max: | 40MHz |
Divider/Multiplier: | No/No |
Voltage - Supply: | 2.97 V ~ 3.63 V |
Operating Temperature: | -40°C ~ 85°C |
Mounting Type: | Surface Mount |
Package / Case: | SOT-23-6 |
Supplier Device Package: | SOT-23-6L |
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The PL902166USY is a clock generator designed for use in various field ranging from communications and computing to audio and video applications. This integrated circuit is characterized by its low power consumption and high output accuracy, as it supports popular synchronization standards such as IEEE1394, S/PDIF, AES/EBU, and I2S. It integrates a spread spectrum phase locked loop (SS PLL) circuit and a low jitter phase locked loop (LJ PLL) circuit, making it suitable for the most demanding applications that require high cross-talk immunity and minimal harmonic distortion at the output.
Application Field
The PL902166USY is suitable for a wide range of applications. Its low power consumption and high output accuracy make it ideal for applications such as digital audio/video receiving/transmitting systems and data transfer networks. It also integrates spread spectrum and low jitter phase locked loop (SS PLL and LJ PLL) circuits, making it suitable for most clock synchronization standards, including IEEE1394, S/PDIF, AES/EBU, and I2S. Moreover, the integrated circuit features a programmable output stage, which allows users to select and customize the optimal output type and frequency.
Working Principle
The PL902166USY is designed to operate according to the spread spectrum phase locked loop (SS PLL) and the low jitter phase locked loop (LJ PLL) principles. The SS PLL is designed to generate a low frequency clock at a given rate. This low frequency clock is then multiplied by a certain factor to generate a higher frequency clock. The output from the SS PLL is then fed into the LJ PLL, which is designed to lock onto the given high frequency clock and generate a low jitter output clock. The output of the LJ PLL is then passed through an output buffer, which is programmed to output the desired frequency and format at the output.
Conclusion
In conclusion, the PL902166USY is a versatile clock generator capable of meeting the most demanding application requirements while consuming minimal power. Its ability to support synchronization standards such as IEEE1394, S/PDIF, AES/EBU, and I2S, makes it ideal for digital audio/video receiving/transmitting systems and data transfer networks. Furthermore, the programmable output stage allows users to select and customize the optimal output type and frequency for their applications.
The specific data is subject to PDF, and the above content is for reference
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