S25FL256SAGMFI001

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1. Description

The Cypress S25FL128S and S25FL256SAGMFI001 devices are flash non-volatile memory products using:

1. MirrorBit technology - that stores two data bits in each memory array transistor

2. Eclipse architecture - that dramatically improves program and erase performance

3. 65 nm process lithography

This family of devices connect to a host system via a SPI. Traditional SPI single bit serial input and output (Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit (Quad I/O or QIO) serial  commands. This multiple width interface is called SPI Multi-I/O or MIO. In addition, the FL-S family adds support for DDR read commands for SIO, DIO, and QIO that transfer address and read data on both edges of the clock. The Eclipse architecture features a Page Programming Buffer that allows up to 128 words (256 bytes) or 256 words (512 bytes) to be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase algorithms. Executing code directly from flash memory is often called Execute-In-Place or XIP. By using FL-S devices at the higher clock rates supported, with QIO or DDR-QIO commands, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, NOR flash memories while reducing signal count dramatically. The S25FL128S and S25FL256S products offer high densities coupled with the flexibility and fast performance required by a variety of embedded applications. They are ideal for code shadowing, XIP, and data storage.

2. Features

    1. CMOS 3.0 Volt Core with Versatile I/O

    2. SPI with Multi-I/O

        - SPI Clock polarity and phase modes 0 and 3

        - DDR option

        - Extended Addressing: 24- or 32-bit address options

        - Serial Command set and footprint compatible with S25FL-A, S25FL-K, and S25FL-P SPI families

        - Multi I/O Command set and footprint compatible with S25FL-P SPI family

    3. READ Commands

        - Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR

        - AutoBoot - power up or reset and execute a Normal or Quad read command automatically at a preselected address

        - Common Flash Interface (CFI) data for configuration information.

    4. Programming (1.5 MBps)

        - 256 or 512 Byte Page Programming buffer options

        - Quad-Input Page Programming (QPP) for slow clock systems

        - Automatic ECC-internal hardware Error Correction Code generation with single bit error correction

    5. Erase (0.5 to 0.65 MBps)

        - Hybrid sector size option - physical set of thirty two 4-KB sectors at top or bottom of address space with all remaining sectors of 64 KB, for compatibility with prior generation S25- FL devices

        - Uniform sector option - always erase 256-KB blocks for software compatibility with higher density and future devices.

    6. Cycling Endurance

        - 100,000 Program-Erase Cycles, minimum

    7. Data Retention

        - 20 Year Data Retention, minimum

    8. Cypress® 65 nm MirrorBit® Technology with Eclipse™ Architecture

    9. Core Supply Voltage: 2.7V to 3.6V

  10. I/O Supply Voltage: 1.65V to 3.6V

        - SO16 and FBGA packages

  11. Temperature Range / Grade:

        - Industrial (-40°C to +85°C)

        - Industrial Plus (-40°C to +105°C)

        - Automotive AEC-Q100 Grade 3 (-40°C to +85°C)

        - Automotive AEC-Q100 Grade 2 (-40°C to +105°C)

        - Automotive AEC-Q100 Grade 1 (-40°C to +125°C)

  12. Packages (all Pb-free)

        - 16-lead SOIC (300 mil)

        - WSON 6 × 8 mm

        - BGA-24 6 × 8 mm

3. Pin configuration

4. Pin description