SI5335B-B08271-GMR

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Introduction

The SI5335B-B08271-GMR is a high performance, ultra-low-jitter, PLL-based clock/timing generator designed to offer a wide range of frequency selections and low EMI (Electro Magnetic Interference). This product is capable of being used in a wide range of applications, from ultra-low-power consumer electronics to high-performance industrial applications. It is a versatile clock/timing solution for those who need accurate frequency generation.

Application Field

The SI5335B-B08271-GMR is a cost-effective, highly integrated PLL-based clock solution for a variety of designs. It supports multiple output frequencies ranging from 6 to 200 MHz with ultra-low jitter of 130 femtoseconds (fs). The clock supports high-input frequencies up to 400 MHz and is targeted for clock generation and jitter attenuation applications such as high-speed digital signal processing (DSP), audio applications such as high-definition television (HDTV), CDMA, satellite, optical switching, servers, communications and security systems, wireless base station timing, and other RF wireless-based applications.

The SI5335B-B08271-GMR is also designed to be a programmable clock generator, allowing multiple output frequencies to be programmed with a single device and offering output frequency flexibility. The device supports spread-spectrum clocking, reducing device power consumption and also provides low-EMI/low-noise outputs. In addition, it supports crystal bypass, providing an extremely low EMI mode.

Working Principle

The SI5335B-B08271-GMR utilizes a digital phase-locked loop (PLL) to synthesize frequency outputs from a single high-frequency reference input and provides a stable, low-jitter clock output. The device incorporates two independent PLLs: a VCO PLL and a reference PLL.

The VCO PLL consists of a voltage-controlled oscillator (VCO), a phase-frequency detect (PFD), and a loop filter comprised of an integrated charge pump and on-chip resistors and capacitors. The PFD generates up/down pulses based on the difference between the VCO output frequency and the reference input frequency. The loop filter generates a control voltage out of the up/down pulses, which is then applied to the VCO to adjust the VCO frequency and thus make the VCO output frequency track the reference input frequency.

The Reference PLL consists of a phase-frequency detect (PFD), a loop filter, and a multiplexer. The Reference PLL manages the multiple output frequencies and locks the VCO to the reference input frequency by controlling the multiplexer switch. Back-bias and spread-spectrum clocking can also be programmed in the device for dithering the output frequency and further reduce EMI noise.

The SI5335B-B08271-GMR also features a divider post-processor and a programmable digital delay line used for generating multiple output frequencies from the VCO frequency.

In summary, the SI5335B-B08271-GMR is a high performance and cost-effective solution for a wide range of applications. It has a wide frequency coverage, ultra-low jitter, excellent frequency stability, and good EMI characteristics, making it an ideal choice for a variety of low-power and high-performance applications.

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