SI5346A-B-GM

Series:	--
Packaging:	Tray
Lead Free Status / RoHS Status:	--
Part Status:	Not For New Designs
Moisture Sensitivity Level (MSL):	--
PLL:	Yes
Input:	LVCMOS, LVDS, LVPECL, Crystal
Output:	CML, HCSL, LVCMOS, LVDS, LVPECL
Number of Circuits:	1
Ratio - Input:Output:	5:4
Differential - Input:Output:	Yes/Yes
Frequency - Max:	712.5MHz
Divider/Multiplier:	Yes/No
Voltage - Supply:	1.71 V ~ 3.47 V
Operating Temperature:	-40°C ~ 85°C
Mounting Type:	Surface Mount
Package / Case:	44-VFQFN Exposed Pad
Supplier Device Package:	44-QFN (7x7)

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SI5346A-B-GM Application Field and Working Principle

The SI5346A-B-GM is a clock generator, phase-locked loop (PLL), and frequency synthesizer IC from Silicon Labs. It allows users to generate, configure, and control multiple synchronous signals on the same board with low-jitter, low-power clock solutions enabling high-speed data throughput. This application note is intended to provide an overview of its applications and working principles.The SI5346A-B-GM is a multi-output clock generator. It integrates a low-noise differential output PLL, 12 independent output drivers and a wide range of output signal formatting features. With its high-frequency reference input, divider and wide process control loop bandwidth, it provides low-jitter output signals with a frequency range from 1MHz to 250MHz and a frequency resolution of 0.1Hz.It is used to generate multiple clock signals for high speed digital systems that require low jitter and low skew. The integrated PLL and multiple output channels of the SI5346A-B-GM makes it an ideal clock solution for applications such as video/ imaging, networking, storage systems, high-definition television, Wi-Fi, Bluetooth, GPS systems, radar and motor control.The SI5346A-B-GM can output multiple synchronous LVDS, LVPECL, HCSL, and SSTL signals with selectable output formats, including differential and single-ended, PECL, LVPECL, RL, and user defined formats. By taking advantage of its wide output frequency range, flexible signal formats and high reference input frequency, this device can easily match a given signal standard and therefore eliminate the need for multiple clock sources.The working principle of the SI5346A-B-GM is founded on the use of a PLL. A PLL is a negative feedback circuit that is designed so that the output signal is a multiple of the input signal frequency. It generates a comparison frequency for the reference input, typically a known clock, and the output signal is adjusted to match the reference input frequency.The clock generator is composed of an oscillator and a divider. The oscillator, or reference clock generator, generates an input frequency that is divided by the divider to produce the comparison frequency. This comparison frequency is then compared to the reference input signal in order to generate the output signal.The current SI5346A-B-GM includes two PLLs, a higher frequency PLL and a lower frequency PLL. The high frequency PLL is used to generate the output signal and the low frequency PLL is used to generate the reference input signal.The PLL contains a phase/frequency detector which produces an error signal proportional to the difference between the output and reference input frequencies. A charge-pump passes this error to the loop filter, where it is integrated and passed to the Voltage-Controlled Oscillator (VCO).The VCO adjusts its output frequency so that the output frequency is equal to the reference input frequency. The frequency of the output signal is determined by the reference input signal frequency and by the settings of the PLLs.Finally, the SI5346A-B-GM outputs the pre-selected format of the clock signal. The outputs can be enabled or disabled as needed, and the frequency and output format can be changed by modifying the settings of the PLLs.In conclusion, the SI5346A-B-GM is an integrated and versatile clock solution that enables low-jitter, robust-signaling and low-power clocks for high-speed data transmission applications. With its high-frequency reference input, divider and wide process control loop bandwidth, it is ideal for generating multiple synchronous and low-jitter clock outputs for a variety of synchronization needs.

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