SI5391D-A-GMR

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The SI5391D-A-GMR clock/timing generator utilizes a Phase-Locked Loop (PLL) architecture in conjunction with proprietary Analog and Digital circuitry to provide a high performance, cost-effective clock source. It is a frequency synthesizer with a number of advantageous features, making it ideal for a range of clock/timing applications. It is a highly integrated device with a 5-channel PLL to simplify board designs, and its performance and versatility lead to shorter time-to-market.

The SI5391D-A-GMR can generate up to five independently adjustable outputs. It supports frequencies of up to 600MHz, providing signal conditioning and jitter reduction in the form of Zero Delay Buffer (ZDB) and Spread Spectrum Clock (SSC) technologies. Sub-band frequencies of up to 10MHz are also supported, along with the capability to embed timing offsets. With its wide range of frequency ranges and multi-channel support, it is ideal for applications such as network system, storage system and communication systems.

The SI5391D-A-GMR is designed to provide a stable output with tight timing tolerances by using a PLL to lock onto an external reference clock. The reference is divided by a frequency divider in order to create a feedback signal that is used to stabilize the output. In order to maintain the internal phase synchronization, the oscillator generates a segmented array of voltage-controlled currents, called the VCO tuning word. This tuning word is then compared to the reference clock and the difference is used to calibrate the PLL over time.

To ensure optimal performance, the SI5391D-A-GMR is supplied with an advanced and highly configurable set of options. These include a range of input options, such as an on-board crystal oscillator, a Temperature Compensated Crystal Oscillator (TCXO) as well as external clock/timing inputs. There is also the ability to select different output line levels, as well as programmable phase margins and slew. Finally, the user can choose between different power management modes and the ability to cascade multiple PLLs.

The SI5391D-A-GMR is designed to facilitate a significant reduction in both emissions and power consumption. In addition, it also leverages a number of features that reduce EMI and RFI for greater board reliability and improved system performance. Finally, the device is supplied in a small form factor, which makes it even more compatible with a wide range of applications. Thus, this makes the SI5391D-A-GMR the ideal choice for a wide range of clock and timing applications where cost, ease-of-use, and reliability are important.

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