SN74AUP2G08DCUR

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1. DESCRIPTION

The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life . This product also maintains excellent signal integrity . This dual 2-input positive-AND gate performs the Boolean function in positive logic. NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

2. FEATURES

    1. Available in the Texas Instruments NanoStar™ Package

    2. Low Static-Power Consumption (ICC = 0.9 mA Max)

    3. Low Dynamic-Power Consumption (Cpd = 4.3 pF Typ at 3.3 V)

    4. Low Input Capacitance (Ci = 1.5 pF Typ)

    5. Low Noise – Overshoot and Undershoot <10% of VCC

    6. Ioff Supports Partial-Power-Down Mode Operation 

    7. Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typ at 3.3 V)

    8. Wide Operating VCC Range of 0.8 V to 3.6 V 

    9. Optimized for 3.3-V Operation

  10. 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation

  11. tpd = 5.9 ns Max at 3.3 V

  12. Suitable for Point-to-Point Applications

  13. Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

  14. ESD Performance Tested Per JESD 22 

        – 2000-V Human-Body Model (A114-B, Class II)

        – 1000-V Charged-Device Model (C101)

3. pin configuration